J. Hicks

3.0k citations

40 papers · 681 · h-index 14

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Radiation Effects in Electronics
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing

Papers in

Electrical and Electronic Engineering 31
- Semiconductor materials and devices 22
- Integrated Circuits and Semiconductor Failure Analysis 17
- Advancements in Semiconductor Devices and Circuit Design 16
- Ferroelectric and Negative Capacitance Devices 6
- Electrostatic Discharge in Electronics 4
- Electronic Packaging and Soldering Technologies 4
Geometry and Topology 8
- Algebraic Geometry and Number Theory 5

Co-authors: S. Ramey (10 shared papers)C. Auth (4 shared papers)C. Prasad (7 shared papers)Robert B. Miller (3 shared papers)Anisur Rahman (3 shared papers)M. Hattendorf (2 shared papers)S. Novak (4 shared papers)R. James (1 shared paper)
Journals: Microelectronics Reliability (1 paper)IEEE Transactions on Device and Materials Reliability (1 paper)Geometry & Topology (1 paper)Journal of Topology (1 paper)Advances in Mathematics (1 paper)
Partner nations: United States United Kingdom Greece

In The Last Decade

J. Hicks

38 papers receiving 652 citations

Peers

Countries citing papers authored by J. Hicks

Since Specialization

Citations

This map shows the geographic impact of J. Hicks's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Hicks with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Hicks more than expected).

Fields of papers citing papers by J. Hicks

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Hicks. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Hicks. The network helps show where J. Hicks may publish in the future.

Co-authors

The 25 scholars most cited alongside J. Hicks, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Hicks Line = papers co-authored together J. Hicks links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

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#	Work
1	Intrinsic transistor reliability improvements from 22nm tri-gate technology S. Ramey, A. Ashutosh, C. Auth, Jason Clifford, M. Hattendorf, J. Hicks, R. James, Anisur Rahman, Varun Sharma, A. St. Amour, C. Wiegand	2013	137
2	Soft Error Rate Improvements in 14-nm Technology Featuring Second-Generation 3D Tri-Gate Transistors IEEE Transactions on Nuclear Science ·N. Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, Ricardo Ascázubi, Nikunj Patel, B. Gill, Joseph M. Basile, J. Hicks	2015	83
3	A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process M. Alavi, M. Bohr, J. Hicks, M. Denham, A. Cassens, D. Douglas, Ming-Yan Tsai	2002	54
4	Microprocessor reliability performance as a function of die location for a 0.25 μ, five layer metal CMOS logic process W.C. Riordan, Robert B. Miller, Jamie Sherman, J. Hicks	2003	49
5	Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology Flavio Griggio, J. Palmer, Fuxiang Pan, Nikholas G. Toledo, A. Schmitz, Ilan Tsameret, Rahim Kasim, G. Leatherman, J. Hicks, Advait Madhavan, Jin-Ho Shin, Joseph M. Steigerwald, A. Yeoh, C. Auth	2018	44
6	Frequency and recovery effects in high-κ BTI degradation S. Ramey, C. Prasad, M. Agostinelli, Sangwoo Pae, S.V. Walstra, Satrajit Gupta, J. Hicks	2009	39
7	Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C. Prasad, M. Agostinelli, J. Hicks, S. Ramey, C. Auth, K. Mistry, S. Natarajan, P. Packan, I. Post, Srinivas Bodapati, M.D. Giles, Sarthak Gupta, S. Mudanai, Kelin J. Kuhn	2014	34
8	Transistor reliability variation correlation to threshold voltage S. Ramey, Manisha Chahal, P. Nayak, S. Novak, C. Prasad, J. Hicks	2015	22
9	BTI recovery in 22nm tri-gate technology S. Ramey, J. Hicks, Luckshitha Suriyasena Liyanage, S. Novak	2014	19
10	eNVM RRAM reliability performance and modeling in 22FFL FinFET technology Yao‐Feng Chang, James A. O'Donnell, Tony Acosta, R. Kotlyar, Albert Chen, Pedro A. Quintero, Nathan Strutt, O. Golonzka, Chris Connor, J. Hicks	2020	17
11	Die-package stress interaction impact on transistor performance G. Leatherman, Jessica Xu, J. Hicks, Bahattin Kilic, Daniel Pantuso	2012	16
12	Aging model challenges in deeply scaled tri-gate technologies S. Ramey, Y.H. Lu, Inanc Meric, S. Mudanai, S. Novak, C. Prasad, J. Hicks	2015	15
13	Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology Sangwoo Pae, C. Prasad, S. Ramey, J. Thomas, Anisur Rahman, Ryan Lu, J. Hicks, S. Batzer, Qingda Zhao, Jonathan Hatfield, M. Liu, C. Parker, B. Woolery	2012	15
14	Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application Anisur Rahman, Peng Bai, G. Curello, J. Hicks, C.-H Jan, Mubasher Jamil, Jang Hyeok Park, K. Phoa, Mustafijur Rahman, C. Tsai, B. Woolery, J.-Y. Yeh	2013	14
15	Modeling Framework for Transistor Aging Playback in Advanced Technology Nodes Inanc Meric, S. Ramey, S. Novak, Sarthak Gupta, S. Mudanai, J. Hicks	2020	13
16	Reliability Characteristics of a High Density Metal- Insulator-Metal Capacitor on Intel’s 10+ Process Che-Yun Lin, Uygar E. Avci, M. A. Blount, R. Grover, J. Hicks, Rahim Kasim, Arun Chandra Kundu, C. Pelto, C. Ryder, A. Schmitz, Kanika Sethi, Dragos Seghete, D. J. Towner, Albert Welsh, J. R. Weber, C. Auth	2020	11
17	Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology Sangwoo Pae, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Maiz, K. Mistry, James A. O'Donnell, C. Prasad, Jami Wiedemer, Jian Xu	2009	10
18	Tropical Lagrangian hypersurfaces are unobstructed Journal of Topology ·J. Hicks	2020	9
19	Characterization and challenge of TDDB reliability in Cu/low K dielectric interconnect Xia Feng, Jun He, Prad Prabhumirashi, A. Schmitz, Anthony Lowrie, J. Hicks, Y. Shusterman, Ruth Brain	2011	8
20	Accelerated stress testing methodology to risk assess silicon-package thermomechanical failure modes resulting from moisture exposure under use condition Scholarworks@UNIST (Ulsan National Institute of Science and Technology) ·S. Rangaraj, Daeil Kwon, Min Pei, J. Hicks, G. Leatherman, Alan Lucero, T.A. Wilson, S. Streit, Jun He	2013	8

About J. Hicks

J. Hicks is a scholar working on Electrical and Electronic Engineering, Geometry and Topology, Electronic, Optical and Magnetic Materials, Mathematical Physics and Computational Theory and Mathematics, having authored 40 papers that have together received 681 indexed citations. Recurring topics across this work include Semiconductor materials and devices (22 papers), Integrated Circuits and Semiconductor Failure Analysis (17 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Ferroelectric and Negative Capacitance Devices (6 papers), Copper Interconnects and Reliability (5 papers), Algebraic Geometry and Number Theory (5 papers), Electrostatic Discharge in Electronics (4 papers) and Electronic Packaging and Soldering Technologies (4 papers). The work is most often cited by research in Hardware and Architecture (93 citations), Electrical and Electronic Engineering (635 citations), Electronic, Optical and Magnetic Materials (56 citations), Geometry and Topology (21 citations) and Safety, Risk, Reliability and Quality (14 citations). J. Hicks has collaborated with scholars based in United States, United Kingdom and Greece. Frequent co-authors include S. Ramey, C. Auth, C. Prasad, Robert B. Miller, Anisur Rahman, M. Hattendorf, S. Novak, R. James, C. Wiegand and A. St. Amour. Their work appears in journals such as Microelectronics Reliability, IEEE Transactions on Device and Materials Reliability, Geometry & Topology, Journal of Topology and Advances in Mathematics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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