I. Post

2.1k citations

30 papers · 1.7k · 1 hit paper · h-index 17

Impact in

Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Silicon and Solar Cell Technologies
Hardware and Architecture top 5%

Papers in

Electrical and Electronic Engineering 30
- Semiconductor materials and devices 23
- Advancements in Semiconductor Devices and Circuit Design 20
- Radio Frequency Integrated Circuit Design 5
- 3D IC and TSV technologies 4
- Silicon Carbide Semiconductor Technologies 4
- Integrated Circuits and Semiconductor Failure Analysis 4
- Thin-Film Transistor Technologies 3
Hardware and Architecture 2

Co-authors: P. Ashburn (10 shared papers)G.R. Wolstenholme (1 shared paper)Paul A. Packan (3 shared papers)Kelin J. Kuhn (4 shared papers)C. J. Gibbings (2 shared papers)D. Becher (1 shared paper)Peter Vandervoorn (1 shared paper)Ian A. Young (1 shared paper)
Journals: IEEE Transactions on Electron Devices (3 papers)Microelectronic Engineering (2 papers)Journal of Applied Physics (1 paper)IEEE Electron Device Letters (1 paper)Electronics Letters (1 paper)
Partner nations: United States United Kingdom

In The Last Decade

I. Post

29 papers receiving 1.6k citations

I. Post's Hit Papers

align trajectories log scale

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors 2012 · 627 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2012 A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Peers

Countries citing papers authored by I. Post

Since Specialization

Citations

This map shows the geographic impact of I. Post's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by I. Post with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites I. Post more than expected).

Fields of papers citing papers by I. Post

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by I. Post. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by I. Post. The network helps show where I. Post may publish in the future.

Co-authors

The 25 scholars most cited alongside I. Post, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with I. Post Line = papers co-authored together I. Post links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 30 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors Chris Auth, Cifford Allen, A. Blattner, D. Bergstrom, Mark Brazier, M. C. Bost, Markus J. Buehler, Vinay Chikarmane Hit paper breakdown →	2012	627
2	A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects Chris Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, Vinay Bhagwat, Jacquelyn Birdsall, Nabhendra Bisnik, Markus J. Buehler	2017	311
3	Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment IEEE Transactions on Electron Devices ·I. Post, P. Ashburn, G.R. Wolstenholme	1992	93
4	Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C. Prasad, Lei Jiang, D. Singh, M. Agostinelli, Chris Auth, Travis M. Eiles, Jeffrey Hicks, C. -H. Jan	2013	76
5	A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications C.-H. Jan, M. Agostinelli, Markus J. Buehler, Zekai Chen, S.-J. Choi, G. Curello, H. Deshpande, S. Gannavaram	2009	67
6	A high performance 180 nm generation logic technology Shih‐Chi Yang, Sally Ahmed, B. Arcot, Reza Arghavani, Pu Bai, S. Chambers, Peter K. Charvat, R. Cotner	2002	60
7	A comparison of state-of-the-art NMOS and SiGe HBT devices for analog/mixed-signal/RF circuit applications Kelin J. Kuhn, R. Basco, D. Becher, M. Hattendorf, Paul A. Packan, I. Post, Peter Vandervoorn, Ian A. Young	2004	49
8	A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications I. Post, M.S. Akbar, G. Curello, S. Gannavaram, W. Hafez, U. Jalan, K. Komeyli, Jiefeng Lin	2006	43
9	A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors C.-H. Jan, S. Biswas, Markus J. Buehler, Zekai Chen, G. Curello, S. Gannavaram, W. Hafez, Jie He	2008	39
10	Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C. Prasad, M. Agostinelli, Jeffrey Hicks, S. Ramey, Chris Auth, Kajal Mistry, S. Natarajan, Paul A. Packan	2014	37
11	Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions IEEE Transactions on Electron Devices ·I. Post, P. Ashburn	1991	36
12	A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors C.-H. Jan, Jaeseok Choi, G. Curello, Steve Jacobs, Jae Woong Jeong, Kevin B. Johnson, Derick Jones, Sabina Beranič Klopčič	2006	33
13	Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing Andrew Yeoh, Advait Madhavan, Nicholas J. Kybert, Srinivasan Anand, Jung H. Shin, M. Asoro, S. Samarajeewa, Joseph M. Steigerwald	2018	33
14	Source/drain extension scaling for 0.1 μm and below channel length MOSFETs Scott E. Thompson, Paul A. Packan, Tahir Ghani, Mark A. Stettler, M. Alavi, I. Post, S. Tyagi, S. Ahmed	2002	30
15	The importance of neutral base recombination in compromising the gain of Si/SiGe heterojunction bipolar transistors IEEE Transactions on Electron Devices ·Z.A. Shafi, C. J. Gibbings, P. Ashburn, I. Post, C. G. Tuppen, D. J. Godfrey	1991	29
16	A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications Yih Wang, Jiefeng Lin, Yat Hon Ng, I. Post, Lin Wei, Yu Zhang, Kedong Zhang, Mark T. Bohr	2007	28
17	A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell Kelin J. Kuhn, M. Agostinelli, Sally Ahmed, S. Chambers, S. Cea, Soren K. Christensen, Paul B. Fischer, J. Gong	2003	27
18	A Reliability Overview of Intel’s 10+ Logic Technology R. Grover, Tony Acosta, C. AnDyke, Emre Armagan, Chris Auth, Sunny Chugh, K. Downes, M. Hattendorf	2020	11
19	Analysis and modeling of the base currents of Si/Si1−xGex heterojunction bipolar transistors fabricated in high and low oxygen content material Journal of Applied Physics ·Z.A. Shafi, P. Ashburn, I. Post, David J. Robbins, Wai Yie Leong, C. J. Gibbings, Sydney Nigrin	1995	9
20	Electrical method for measuring emitter depth of shallow bipolar transistors Electronics Letters ·I. Post, P. Ashburn	1990	5

About I. Post

I. Post is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Atomic and Molecular Physics, and Optics, Electronic, Optical and Magnetic Materials and Materials Chemistry, having authored 30 papers that have together received 1.7k indexed citations. Recurring topics across this work include Semiconductor materials and devices (23 papers), Advancements in Semiconductor Devices and Circuit Design (20 papers), Radio Frequency Integrated Circuit Design (5 papers), 3D IC and TSV technologies (4 papers), Silicon Carbide Semiconductor Technologies (4 papers), Integrated Circuits and Semiconductor Failure Analysis (4 papers), Semiconductor materials and interfaces (4 papers) and Thin-Film Transistor Technologies (3 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.6k citations), Hardware and Architecture (123 citations), Atomic and Molecular Physics, and Optics (182 citations), Biomedical Engineering (194 citations) and Materials Chemistry (172 citations). I. Post has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include P. Ashburn, G.R. Wolstenholme, Paul A. Packan, Kelin J. Kuhn, C. J. Gibbings, D. Becher, Peter Vandervoorn, Ian A. Young, M. Hattendorf and W. Hafez. Their work appears in journals such as IEEE Transactions on Electron Devices, Microelectronic Engineering, Journal of Applied Physics, IEEE Electron Device Letters and Electronics Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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