C. Tsai

880 citations

14 papers · 735 · h-index 11

Impact in

Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Radio Frequency Integrated Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Silicon Carbide Semiconductor Technologies
Hardware and Architecture top 10%

Papers in

Electrical and Electronic Engineering 14
- Semiconductor materials and devices 13
- Advancements in Semiconductor Devices and Circuit Design 11
- Integrated Circuits and Semiconductor Failure Analysis 6
- Radio Frequency Integrated Circuit Design 3
- Silicon Carbide Semiconductor Technologies 2
- Low-power high-performance VLSI design 2
- 3D IC and TSV technologies 1
- Advancements in Photolithography Techniques 1
Surfaces, Coatings and Films 1

Co-authors: W. Hafez (4 shared papers)Jang Hyeok Park (3 shared papers)G. Curello (3 shared papers)K. Komeyli (3 shared papers)C.-H. Jan (2 shared papers)Jiefeng Lin (1 shared paper)David A. Yeh (1 shared paper)M.S. Akbar (1 shared paper)
Partner nations: United States

In The Last Decade

C. Tsai

14 papers receiving 716 citations

Peers

Countries citing papers authored by C. Tsai

Since Specialization

Citations

This map shows the geographic impact of C. Tsai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Tsai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Tsai more than expected).

Fields of papers citing papers by C. Tsai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Tsai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Tsai. The network helps show where C. Tsai may publish in the future.

Co-authors

The 25 scholars most cited alongside C. Tsai, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with C. Tsai Line = papers co-authored together C. Tsai links everyone, so they are left out of the graph.

All Works

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14 of 14 papers shown

#	Work
1	A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications C.-H. Jan, Uma Bhattacharya, R. Brain, S.-J. Choi, G. Curello, Garima Gupta, W. Hafez, Min-Seo Jang	2012	266
2	RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications C.-H. Jan, M. Agostinelli, H. Deshpande, Mohamed El‐Tanani, W. Hafez, U. Jalan, L. Janbay, Myounggon Kang	2010	77
3	Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C. Prasad, Lei Jiang, D. Singh, M. Agostinelli, Chris Auth, Travis M. Eiles, Jeffrey Hicks, C. -H. Jan	2013	76
4	A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications C.-H. Jan, M. Agostinelli, Markus J. Buehler, Zekai Chen, S.-J. Choi, G. Curello, H. Deshpande, S. Gannavaram	2009	67
5	A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications I. Post, M.S. Akbar, G. Curello, S. Gannavaram, W. Hafez, U. Jalan, K. Komeyli, Jiefeng Lin	2006	43
6	A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products C.-H. Jan, F. Al-Amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, Neville L. Dias, W. Hafez, Doug B. Ingerly	2015	42
7	Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing W. Hafez, Prashant Agnihotri, M. Asoro, Muratahan Aykol, Balijeet Bains, R. Bambery, Mukund Bapna, Amar Kumar Barik	2023	39
8	A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors C.-H. Jan, S. Biswas, Markus J. Buehler, Zekai Chen, G. Curello, S. Gannavaram, W. Hafez, Jie He	2008	39
9	A 32nm low power RF CMOS SOC technology featuring high-k/metal gate Peter Vandervoorn, M. Agostinelli, S.-J. Choi, G. Curello, H. Deshpande, Mohamed El‐Tanani, W. Hafez, U. Jalan	2010	30
10	Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms C. Prasad, K. W. Park, Manisha Chahal, Inanc Meric, Steven R. Novak, S. Ramey, H.-Y. Chang, Neville L. Dias	2016	22
11	Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application Anisur Rahman, G. Curello, Jeffrey Hicks, C.-H Jan, Mubasher Jamil, Jang Hyeok Park, Kinyip Phoa, Mustafijur Rahman	2013	17
12	Reliability studies of a 32nm System-on-Chip (SoC) platform technology with 2nd generation high-k/metal gate transistors Anisur Rahman, M. Agostinelli, G. Curello, H. Deshpande, W. Hafez, C. -H. Jan, K. Komeyli, Jang Hyeok Park	2011	10
13	Reliability studies on a 45nm low power system-on-chip (SoC) dual gate oxide high-k / metal gate (DG HK+MG) technology C. Prasad, S. Gannavaram, W. Hafez, Jeffrey Hicks, C.-H. Jan, Jyi-Tsong Lin, Matthew Jones, K. Komeyli	2010	5
14	E-beam inspection for gap physical defect detection in 28nm CMOS process Tsung Chih Chen, C. Tsai, White Pai, Curious Wu, Fei Wang +1 other	2013	2

About C. Tsai

C. Tsai is a scholar working on Electrical and Electronic Engineering, Surfaces, Coatings and Films, Condensed Matter Physics, Insect Science and Renewable Energy, Sustainability and the Environment, having authored 14 papers that have together received 735 indexed citations. Recurring topics across this work include Semiconductor materials and devices (13 papers), Advancements in Semiconductor Devices and Circuit Design (11 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Radio Frequency Integrated Circuit Design (3 papers), Silicon Carbide Semiconductor Technologies (2 papers), Low-power high-performance VLSI design (2 papers), 3D IC and TSV technologies (1 paper) and Advancements in Photolithography Techniques (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (691 citations), Hardware and Architecture (65 citations), Biomedical Engineering (77 citations), Materials Chemistry (59 citations) and Atomic and Molecular Physics, and Optics (37 citations). C. Tsai has collaborated with scholars based in United States. Frequent co-authors include W. Hafez, Jang Hyeok Park, G. Curello, K. Komeyli, C.-H. Jan, Jiefeng Lin, David A. Yeh, M.S. Akbar, N. Lindert and Jad B. Rizk.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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C. Tsai

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