A. Murthy

3.8k citations

13 papers · 1.6k · h-index 12

Impact in

Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Ferroelectric and Negative Capacitance Devices
- Silicon and Solar Cell Technologies
Biomedical Engineering top 10%
- Nanowire Synthesis and Applications

Papers in

Electrical and Electronic Engineering 12
- Semiconductor materials and devices 12
- Advancements in Semiconductor Devices and Circuit Design 12
- Integrated Circuits and Semiconductor Failure Analysis 3
- Silicon Carbide Semiconductor Technologies 3
- Ferroelectric and Negative Capacitance Devices 1
Biomedical Engineering 4
- Nanowire Synthesis and Applications 4

Co-authors: R. Chau (6 shared papers)J. Kavalieros (6 shared papers)T. Ghani (4 shared papers)M. Doczy (4 shared papers)M. Bohr (3 shared papers)K. Mistry (3 shared papers)C. Auth (3 shared papers)M Armstrong (3 shared papers)
Journals: IEEE Electron Device Letters (2 papers)SAE technical papers on CD-ROM/SAE technical paper series (1 paper)ECS Transactions (1 paper)ECS Meeting Abstracts (1 paper)
Partner nations: United States United Kingdom India

In The Last Decade

A. Murthy

13 papers receiving 1.5k citations

Peers

Countries citing papers authored by A. Murthy

Since Specialization

Citations

This map shows the geographic impact of A. Murthy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Murthy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Murthy more than expected).

Fields of papers citing papers by A. Murthy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Murthy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Murthy. The network helps show where A. Murthy may publish in the future.

Co-authors

The 25 scholars most cited alongside A. Murthy, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with A. Murthy Line = papers co-authored together A. Murthy links everyone, so they are left out of the graph.

All Works

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13 of 13 papers shown

#	Work
1	A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters ·Scott E. Thompson, M Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. W. Klaus, Zhenqiang Ma, B. McIntyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, Y.A. El-Mansy	2004	389
2	A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors T. Ghani, M Armstrong, C. Auth, M. Bost, P. Charvát, G. Glass, Thomas Hoffmann, Kevin B. Johnson, C. Kenyon, J. W. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, Meredith N. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, Scott E. Thompson, M. Bohr	2004	378
3	High performance fully-depleted tri-gate CMOS transistors IEEE Electron Device Letters ·B.S. Doyle, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau	2003	324
4	Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology K. Mistry, M Armstrong, C. Auth, S. Cea, Tom Coan, T. Ghani, Thomas Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, Kedong Zhang, Scott E. Thompson, M. Bohr	2004	114
5	30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays R. Chau, J. Kavalieros, B. Roberds, Richard E. Schenker, D. Lionberger, Douglas W. Barlage, Barry M. Doyle, Reza Arghavani, A. Murthy, G. Dewey	2002	81
6	A 50 nm depleted-substrate CMOS transistor (DST) R. Chau, J. Kavalieros, Barry M. Doyle, A. Murthy, N. Paulsen, D. Lionberger, Douglas W. Barlage, Reza Arghavani, B. Roberds, M. Doczy	2002	73
7	(Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling ECS Transactions ·Kelin J. Kuhn, A. Murthy, R. Kotlyar, Markus Kühn	2010	63
8	Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate R. Chau, B.S. Doyle, J. Kavalieros, Doug Barlage, A. Murthy, M. Doczy, Reza Arghavani, Suman Datta	2002	49
9	High performance Hi-K + metal gate strain enhanced transistors on (110) silicon P. Packan, S. Cea, H. Deshpande, T. Ghani, M.D. Giles, O. Golonzka, M. Hattendorf, R. Kotlyar, Kelin J. Kuhn, A. Murthy, P. Ranade, L. Shifren, C. Weber, K. Zawadzki	2008	44
10	Gate-All-Around Strained Si_0.4Ge_0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application Ankur Agrawal, S. Chouksey, W. Rachmady, Suresh Vishwanath, Srabantika Ghose, M. Mehta, J. Torres, A. Oni, X. Weng, H. Li, Devin R. Merrill, M. Metz, A. Murthy, J. Kavalieros	2020	40
11	High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics Douglas W. Barlage, Reza Arghavani, G. Dewey, M. Doczy, Barry M. Doyle, J. Kavalieros, A. Murthy, B. Roberds, P. Stokley, R. Chau	2002	29
12	Past, Present and Future: SiGe and CMOS Transistor Scaling ECS Meeting Abstracts ·Kelin J. Kuhn, A. Murthy	2010	22
13	Improvement in Noise Transmission Across Firewall of a Passenger Car SAE technical papers on CD-ROM/SAE technical paper series ·Smita Shivle, A. Murthy	2010	2

About A. Murthy

A. Murthy is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Computer Networks and Communications, Civil and Structural Engineering and Control and Systems Engineering, having authored 13 papers that have together received 1.6k indexed citations. Recurring topics across this work include Semiconductor materials and devices (12 papers), Advancements in Semiconductor Devices and Circuit Design (12 papers), Nanowire Synthesis and Applications (4 papers), Integrated Circuits and Semiconductor Failure Analysis (3 papers), Silicon Carbide Semiconductor Technologies (3 papers), Transportation Safety and Impact Analysis (1 paper), Internet of Things and Social Network Interactions (1 paper) and Ferroelectric and Negative Capacitance Devices (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (1.5k citations), Biomedical Engineering (415 citations), Structural Biology (13 citations), Atomic and Molecular Physics, and Optics (204 citations) and Materials Chemistry (191 citations). A. Murthy has collaborated with scholars based in United States, United Kingdom and India. Frequent co-authors include R. Chau, J. Kavalieros, T. Ghani, M. Doczy, M. Bohr, K. Mistry, C. Auth, M Armstrong, Scott E. Thompson and B. McIntyre. Their work appears in journals such as IEEE Electron Device Letters, SAE technical papers on CD-ROM/SAE technical paper series, ECS Transactions and ECS Meeting Abstracts.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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A. Murthy

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