P. Ranade

2.8k citations

38 papers · 2.2k · 1 hit paper · h-index 18

Impact in

Electrical and Electronic Engineering top 1%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
Atomic and Molecular Physics, and Optics top 10%
- Semiconductor materials and interfaces

Papers in

Electrical and Electronic Engineering 36
- Advancements in Semiconductor Devices and Circuit Design 26
- Semiconductor materials and devices 22
- Low-power high-performance VLSI design 3
Atomic and Molecular Physics, and Optics 14
- Semiconductor materials and interfaces 13
- Surface and Thin Film Phenomena 1

Co-authors: Tsu‐Jae King (27 shared papers)Chenming Calvin Hu (18 shared papers)I. Polishchuk (5 shared papers)Hideki Takeuchi (13 shared papers)Yee‐Chia Yeo (7 shared papers)Qiang Lu (4 shared papers)Daewon Ha (5 shared papers)R. Lin (4 shared papers)
Journals: IEEE Electron Device Letters (6 papers)Electrochemical and Solid-State Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)Applied Surface Science (1 paper)Japanese Journal of Applied Physics (1 paper)
Partner nations: United States Japan Taiwan

In The Last Decade

P. Ranade

37 papers receiving 2.1k citations

P. Ranade's Hit Papers

align trajectories log scale

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging 2007 · 653 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2007 Technical digest - International Electron Devices Meeting/Technical digest

Peers

Countries citing papers authored by P. Ranade

Since Specialization

Citations

This map shows the geographic impact of P. Ranade's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Ranade with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Ranade more than expected).

Fields of papers citing papers by P. Ranade

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Ranade. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Ranade. The network helps show where P. Ranade may publish in the future.

Co-authors

The 25 scholars most cited alongside P. Ranade, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with P. Ranade Line = papers co-authored together P. Ranade links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 38 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging Technical digest - International Electron Devices Meeting/Technical digest ·Kajal Mistry, Robert S. Chau, Changhwan Choi, G. Ding, K. Fischer, Tahir Ghani, R. Grover, Won Seok Han Hit paper breakdown →	2007	653
2	Extremely scaled silicon nano-CMOS devices Proceedings of the IEEE ·Leland Chang, Yang‐Kyu Choi, Daewon Ha, P. Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Calvin Hu, Tsu‐Jae King	2003	219
3	An adjustable work function technology using Mo gate for CMOS devices IEEE Electron Device Letters ·R. Lin, Qiang Lu, P. Ranade, Tsu‐Jae King, Chenming Calvin Hu	2002	165
4	45nm High-k + metal gate strain-enhanced transistors Symposium on VLSI Technology ·Chris Auth, A. Cappellani, Adam Dalis, Tahir Ghani, G. Glass, Timothy E. Glassman, Maddie Harper, M. Hattendorf	2008	157
5	Dual work function metal gate CMOS technology using metal interdiffusion IEEE Electron Device Letters ·I. Polishchuk, P. Ranade, Tsu‐Jae King, Chenming Calvin Hu	2001	152
6	Effects of high-/spl kappa/ gate dielectric materials on metal and silicon gate workfunctions IEEE Electron Device Letters ·Yee‐Chia Yeo, P. Ranade, Tsu‐Jae King, Chenming Calvin Hu	2002	145
7	Work Function Engineering of Molybdenum Gate Electrodes by Nitrogen Implantation Electrochemical and Solid-State Letters ·P. Ranade, Hideki Takeuchi, Tsu‐Jae King, Chenming Calvin Hu	2001	103
8	FinFET process refinements for improved mobility and gate work function engineering KAIST Institutional Repository (KAIST) ·Yang‐Kyu Choi, Leland Chang, P. Ranade, Daewon Ha, Sandhana Balasubramanian, Aditya Agarwal, M. S. Ameen, Tsu‐Jae King	2003	89
9	Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric IEEE Electron Device Letters ·Yee‐Chia Yeo, Qiang Lu, P. Ranade, Hideki Takeuchi, Kevin J. Yang, I. Polishchuk, Tsu‐Jae King, Chenming Calvin Hu	2001	81
10	Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion IEEE Electron Device Letters ·I. Polishchuk, P. Ranade, Tsu‐Jae King, Chenming Calvin Hu	2002	67
11	High performance Hi-K + metal gate strain enhanced transistors on (110) silicon Technical digest - International Electron Devices Meeting/Technical digest ·Paul A. Packan, S. Cea, H. Deshpande, Tahir Ghani, Martin D. Giles, Oleg Golonzka, M. Hattendorf, R. Kotlyar	2008	49
12	Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications Technical digest - International Electron Devices Meeting/Technical digest ·K. Fujita, Y. Torii, Mitsuaki Hori, Jungwoo Oh, L. Shifren, P. Ranade, Takushi Miyake, K. Ohkoshi	2011	47
13	Tunable work function molybdenum gate technology for FDSOI-CMOS KAIST Institutional Repository (KAIST) ·P. Ranade, Yang‐Kyu Choi, Daewon Ha, Aditya Agarwal, M. S. Ameen, Tsu‐Jae King	2003	37
14	Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology MRS Proceedings ·P. Ranade, Yee‐Chia Yeo, Qiang Lü, Hideki Takeuchi, Tsu‐Jae King, Chenming Calvin Hu	2000	32
15	Dual-metal gate technology for deep-submicron CMOS transistors Symposium on VLSI Technology ·Qiang Lu, Yee‐Chia Yeo, P. Ranade, Hideki Takeuchi, Tsu‐Jae King, Chenming Calvin Hu, Sook‐Keun Song, H.F. Luan	2002	32
16	Metal gate work function adjustment for future CMOS technology Symposium on VLSI Technology ·Qiang Lü, R. Lin, P. Ranade, Tsu‐Jae King, Chenming Calvin Hu	2002	31
17	Observation of dopant-mediated intermixing at Ge/Si Interface Applied Physics Letters ·Hideki Takeuchi, P. Ranade, Vivek Subramanian, Tsu‐Jae King	2002	23
18	A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits Technical digest - International Electron Devices Meeting/Technical digest ·Lawrence T. Clark, Daniel Zhao, Teymur Bakhishev, Hong Jo Ahn, Edward Boling, Michael P. Duane, K. Fujita, Paul E. Gregory	2012	19
19	Effects of high-κ dielectrics on the workfunctions of metal and silicon gates Symposium on VLSI Technology ·Yee‐Chia Yeo, P. Ranade, Qiang Lü, R. Lin, Tsu‐Jae King, Chenming Calvin Hu	2002	18
20	30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D Yang‐Kyu Choi, Yoo-Chan Jeon, P. Ranade, H. Takenuchi, Tsu‐Jae King, Jeffrey Bokor, Chenming Calvin Hu	2002	17

About P. Ranade

P. Ranade is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Condensed Matter Physics, Electronic, Optical and Magnetic Materials and Materials Chemistry, having authored 38 papers that have together received 2.2k indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (26 papers), Semiconductor materials and devices (22 papers), Semiconductor materials and interfaces (13 papers), Low-power high-performance VLSI design (3 papers), Solidification and crystal growth phenomena (1 paper), Copper Interconnects and Reliability (1 paper), Surface and Thin Film Phenomena (1 paper) and Theoretical and Computational Physics (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (2k citations), Atomic and Molecular Physics, and Optics (258 citations), Hardware and Architecture (51 citations), Bioengineering (11 citations) and Materials Chemistry (118 citations). P. Ranade has collaborated with scholars based in United States, Japan and Taiwan. Frequent co-authors include Tsu‐Jae King, Chenming Calvin Hu, I. Polishchuk, Hideki Takeuchi, Yee‐Chia Yeo, Qiang Lu, Daewon Ha, R. Lin, Jeffrey Bokor and Leland Chang. Their work appears in journals such as IEEE Electron Device Letters, Electrochemical and Solid-State Letters, IEEE Transactions on Electron Devices, Applied Surface Science and Japanese Journal of Applied Physics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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P. Ranade's Hit Papers

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