R. Chau

7.9k citations

57 papers · 4.8k · 1 hit paper · h-index 34

Impact in

Electrical and Electronic Engineering top 0.5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
Biomedical Engineering top 2%
- Nanowire Synthesis and Applications

Papers in

Electrical and Electronic Engineering 55
- Semiconductor materials and devices 52
- Advancements in Semiconductor Devices and Circuit Design 51
- Ferroelectric and Negative Capacitance Devices 9
- Integrated Circuits and Semiconductor Failure Analysis 9
- Silicon Carbide Semiconductor Technologies 2
Biomedical Engineering 20
- Nanowire Synthesis and Applications 20

Co-authors: J. Kavalieros (27 shared papers)Suman Datta (19 shared papers)M. Doczy (16 shared papers)M. Metz (17 shared papers)B.S. Doyle (6 shared papers)Barry M. Doyle (10 shared papers)M. Bohr (4 shared papers)G. Dewey (20 shared papers)
Journals: IEEE Electron Device Letters (6 papers)IEEE Transactions on Electron Devices (3 papers)Microelectronic Engineering (1 paper)Nature Materials (1 paper)Electronics Letters (1 paper)
Partner nations: United States United Kingdom Sweden

In The Last Decade

R. Chau

56 papers receiving 4.5k citations

R. Chau's Hit Papers

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Benchmarking nanotechnology for high-performance and low power logic transistor applications 2005 · 485 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2005 Benchmarking nanotechnology for high-performance and low power logic transistor applications

Peers

Countries citing papers authored by R. Chau

Since Specialization

Citations

This map shows the geographic impact of R. Chau's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by R. Chau with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites R. Chau more than expected).

Fields of papers citing papers by R. Chau

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by R. Chau. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by R. Chau. The network helps show where R. Chau may publish in the future.

Co-authors

The 25 scholars most cited alongside R. Chau, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with R. Chau Line = papers co-authored together R. Chau links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 57 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Benchmarking nanotechnology for high-performance and low power logic transistor applications R. Chau Hit paper breakdown →	2005	485
2	A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters ·Scott E. Thompson, M Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. W. Klaus, Zhenqiang Ma, B. McIntyre, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, Y.A. El-Mansy	2004	389
3	High-<tex>$kappa$</tex>/Metal–Gate Stack and Its MOSFET Characteristics IEEE Electron Device Letters ·R. Chau, Suman Datta, M. Doczy, Barry M. Doyle, J. Kavalieros, M. Metz	2004	369
4	Integrated nanoelectronics for the future Nature Materials ·R. Chau, B.S. Doyle, Suman Datta, J. Kavalieros, Kevin S. Zhang	2007	329
5	High performance fully-depleted tri-gate CMOS transistors IEEE Electron Device Letters ·B.S. Doyle, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau	2003	327
6	The High-k Solution IEEE Spectrum ·M. Bohr, R. Chau, T. Ghani, Kaizad Mistry	2007	286
7	Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu, D. Lubyshev, M. Metz, Niloy Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljević, Han Wui Then, R. Chau	2011	282
8	Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering J. Kavalieros, Barry M. Doyle, Suman Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljević, Uday Shah, N. Zelick, R. Chau	2006	178
9	Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout Barry M. Doyle, B. I. Boyanov, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau	2004	163
10	In Search of “Forever,” Continued Transistor Scaling One New Material at a Time IEEE Transactions on Semiconductor Manufacturing ·Scott E. Thompson, R. Chau, T. Ghani, K. Mistry, S. Tyagi, M. Bohr	2005	119
11	Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation M. Radosavljević, G. Dewey, Dipanjan Basu, J. Boardman, B. Chu-Kung, J. M. Fastenau, Sanaz Kabehie, J. Kavalieros, Hung V. Le, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, Niloy Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, Uday Shah, Han Wui Then, R. Chau	2011	117
12	Advanced high-K gate dielectric for high-performance short-channel In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum well field effect transistors on silicon substrate for low power logic applications M. Radosavljević, B. Chu-Kung, S. Corcoran, G. Dewey, Mantu K. Hudait, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, Niloy Mukherjee, W. Rachmady, Uday Shah, R. Chau	2009	111
13	Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology Microelectronic Engineering ·R. Chau, J.K. Brask, Suman Datta, G. Dewey, M. Doczy, B.S. Doyle, J. Kavalieros, B. Jin, M. Metz, Amlan Majumdar, M. Radosavljević	2005	105
14	Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications Electronics Letters ·T. Ashley, L. Buckle, Suman Datta, M. T. Emeny, D.G. Hayes, K.P. Hilton, Richard Jefferies, Trevor Martin, T. J. Phillips, D. J. Wallis, P.J. Wilding, R. Chau	2007	92
15	85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications ORCA Online Research @Cardiff (Cardiff University) ·Suman Datta, T. Ashley, J.K. Brask, L. Buckle, M. Doczy, M. T. Emeny, D.G. Hayes, K.P. Hilton, Richard Jefferies, Trevor Martin, T. J. Phillips, D. J. Wallis, Peter Wilding, R. Chau	2006	90
16	Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications R. Chau, Suman Datta, A. Majumdar	2005	86
17	30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays R. Chau, J. Kavalieros, B. Roberds, Richard E. Schenker, D. Lionberger, Douglas W. Barlage, Barry M. Doyle, Reza Arghavani, A. Murthy, G. Dewey	2002	81
18	High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture R. Pillarisetty, B. Chu-Kung, S. Corcoran, G. Dewey, J. Kavalieros, Harold Kennel, R. Kotlyar, Hung V. Le, D. Lionberger, M. Metz, Niloy Mukherjee, Junghyo Nah, W. Rachmady, M. Radosavljević, Uday Shah, S. Taft, Han Wui Then, N. Zelick, R. Chau	2010	80
19	Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications M. Radosavljević, G. Dewey, J. M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, D. Lubyshev, M. Metz, K. Millard, Niloy Mukherjee, L. Pan, R. Pillarisetty, W. Rachmady, Uday Shah, R. Chau	2010	78
20	A 50 nm depleted-substrate CMOS transistor (DST) R. Chau, J. Kavalieros, Barry M. Doyle, A. Murthy, N. Paulsen, D. Lionberger, Douglas W. Barlage, Reza Arghavani, B. Roberds, M. Doczy	2002	74

About R. Chau

R. Chau is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Atomic and Molecular Physics, and Optics, Electronic, Optical and Magnetic Materials and Materials Chemistry, having authored 57 papers that have together received 4.8k indexed citations. Recurring topics across this work include Semiconductor materials and devices (52 papers), Advancements in Semiconductor Devices and Circuit Design (51 papers), Nanowire Synthesis and Applications (20 papers), Ferroelectric and Negative Capacitance Devices (9 papers), Integrated Circuits and Semiconductor Failure Analysis (9 papers), Semiconductor Quantum Structures and Devices (5 papers), Ga2O3 and related materials (3 papers) and Silicon Carbide Semiconductor Technologies (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (4.4k citations), Biomedical Engineering (1.4k citations), Atomic and Molecular Physics, and Optics (907 citations), Materials Chemistry (954 citations) and Condensed Matter Physics (137 citations). R. Chau has collaborated with scholars based in United States, United Kingdom and Sweden. Frequent co-authors include J. Kavalieros, Suman Datta, M. Doczy, M. Metz, B.S. Doyle, Barry M. Doyle, M. Bohr, G. Dewey, T. Ghani and M. Radosavljević. Their work appears in journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, Microelectronic Engineering, Nature Materials and Electronics Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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R. Chau

R. Chau's Hit Papers

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All Works

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