S.A. Hareland

1.8k citations

34 papers · 1.5k · h-index 16

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design

Papers in

Electrical and Electronic Engineering 29
- Semiconductor materials and devices 27
- Advancements in Semiconductor Devices and Circuit Design 23
- Radiation Effects in Electronics 7
- Integrated Circuits and Semiconductor Failure Analysis 6
- Silicon Carbide Semiconductor Technologies 5
Atomic and Molecular Physics, and Optics 7
- Quantum and electron transport phenomena 6

Co-authors: J. Maiz (6 shared papers)Peter R. Armstrong (2 shared papers)R. Chau (5 shared papers)M. Doczy (4 shared papers)J. Kavalieros (4 shared papers)Suman Datta (4 shared papers)B. Jin (4 shared papers)A.F. Tasch (15 shared papers)
Journals: IEEE Transactions on Electron Devices (8 papers)IEEE Electron Device Letters (3 papers)IEEE Transactions on Device and Materials Reliability (1 paper)Electronics Letters (1 paper)VLSI design (1 paper)
Partner nations: United States United Kingdom

In The Last Decade

S.A. Hareland

31 papers receiving 1.3k citations

Peers

Countries citing papers authored by S.A. Hareland

Since Specialization

Citations

This map shows the geographic impact of S.A. Hareland's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S.A. Hareland with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S.A. Hareland more than expected).

Fields of papers citing papers by S.A. Hareland

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S.A. Hareland. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S.A. Hareland. The network helps show where S.A. Hareland may publish in the future.

Co-authors

The 25 scholars most cited alongside S.A. Hareland, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S.A. Hareland Line = papers co-authored together S.A. Hareland links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 34 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	High performance fully-depleted tri-gate CMOS transistors IEEE Electron Device Letters ·B.S. Doyle, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau	2003	346
2	Characterization of multi-bit soft error events in advanced SRAMs J. Maiz, S.A. Hareland, Kedong Zhang, Peter R. Armstrong	2004	202
3	Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout Barry M. Doyle, B. I. Boyanov, Suman Datta, M. Doczy, S.A. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau	2004	174
4	Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation P. Hazucha, Tanay Karnik, J. Maiz, S.V. Walstra, B. Bloechel, James Tschanz, G. Dermer, S.A. Hareland, Peter R. Armstrong, Shekhar Borkar	2004	125
5	Impact of CMOS process scaling and SOI on the soft error rates of logic processes S.A. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta, Changhong Dai	2002	96
6	A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFETs IEEE Transactions on Electron Devices ·S.A. Hareland, Srini Krishnamurthy, S. Jallepalli, Choh-Fei Yeap, K. Hasnat, A.F. Tasch, C.M. Maziar	1996	85
7	Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers IEEE Electron Device Letters ·G. Chindalore, S.A. Hareland, S. Jallepalli, A.F. Tasch, C.M. Maziar, Victor K. F. Chia, Stephen P. Smith	1997	65
8	A pseudo-lucky electron model for simulation of electron gate current in submicron NMOSFET's IEEE Transactions on Electron Devices ·K. Hasnat, Choh-Fei Yeap, S. Jallepalli, W.-K. Shih, S.A. Hareland, V.M. Agostinelli, A.F. Tasch, C.M. Maziar	1996	59
9	Silicon nano-transistors and breaking the 10 nm physical gate length barrier R. Chau, Barry M. Doyle, M. Doczy, Suman Datta, S.A. Hareland, B. Jin, J. Kavalieros, M. Metz	2004	41
10	Silicon nano-transistors for logic applications Physica E Low-dimensional Systems and Nanostructures ·R. Chau, B. I. Boyanov, B.S. Doyle, M. Doczy, Suman Datta, S.A. Hareland, B. Jin, J. Kavalieros, M. Metz	2003	38
11	Thermionic emission model of electron gate current in submicron NMOSFETs IEEE Transactions on Electron Devices ·K. Hasnat, Choh-Fei Yeap, S. Jallepalli, S.A. Hareland, W.-K. Shih, V.M. Agostinelli, A.F. Tasch, C.M. Maziar	1997	35
12	Computationally efficient models for quantization effects in MOS electron and hole accumulation layers IEEE Transactions on Electron Devices ·S.A. Hareland, M. Manassian, W.-K. Shih, S. Jallepalli, H. Wang, G. Chindalore, A.F. Tasch, C.M. Maziar	1998	27
13	A cautionary tale of soft errors induced by SRAM packaging materials IEEE Transactions on Device and Materials Reliability ·Jeff Wilkinson, S.A. Hareland	2005	24
14	New structural approach for reducing punchthrough current in deep submicrometre MOSFETs and extending MOSFET scaling Electronics Letters ·S.A. Hareland, A.F. Tasch, C.M. Maziar	1993	22
15	A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS devices IEEE Transactions on Electron Devices ·S.A. Hareland, S. Jallepalli, G. Chindalore, W.-K. Shih, A.F. Tasch, C.M. Maziur	1997	19
16	A physically-based model for quantization effects in hole inversion layers IEEE Transactions on Electron Devices ·S.A. Hareland, S. Jallepalli, Wei-Kai Shih, Haihong Wang, G. Chindalore, A.F. Tasch, C.M. Maziar	1998	17
17	Experimental determination of electron and hole mobilities in MOS accumulation layers IEEE Electron Device Letters ·J.B. McKeon, G. Chindalore, S.A. Hareland, W.-K. Shih, C. Wang, A.F. Tasch, C.M. Maziar	1997	15
18	Reliability considerations for implantable medical ICs Mark Porter, Paul Gerrish, Larry Tyler, Sharon Murray, Rob Mauriello, Frank Soto, G. E. Phetteplace, S.A. Hareland	2008	13
19	Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMOS technology Changhong Dai, (unknown), S.A. Hareland, J. Maiz, Shiuh-Wuu Lee	1999	12
20	An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers IEEE Transactions on Electron Devices ·G. Chindalore, J.B. McKeon, S. Mudanai, S.A. Hareland, W.-K. Shih, C. Wang, A.F. Tasch, C.M. Maziar	1998	10

About S.A. Hareland

S.A. Hareland is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Biomedical Engineering, Hardware and Architecture and Medical Laboratory Technology, having authored 34 papers that have together received 1.5k indexed citations. Recurring topics across this work include Semiconductor materials and devices (27 papers), Advancements in Semiconductor Devices and Circuit Design (23 papers), Radiation Effects in Electronics (7 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Quantum and electron transport phenomena (6 papers), Silicon Carbide Semiconductor Technologies (5 papers), VLSI and Analog Circuit Testing (3 papers) and Quality and Safety in Healthcare (3 papers). The work is most often cited by research in Hardware and Architecture (275 citations), Electrical and Electronic Engineering (1.4k citations), Biomedical Engineering (218 citations), Atomic and Molecular Physics, and Optics (153 citations) and Software (15 citations). S.A. Hareland has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include J. Maiz, Peter R. Armstrong, R. Chau, M. Doczy, J. Kavalieros, Suman Datta, B. Jin, A.F. Tasch, Kedong Zhang and T. Linton. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Device and Materials Reliability, Electronics Letters and VLSI design.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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