S. Cea

2.1k citations

25 papers · 1.6k · 1 hit paper · h-index 11

Impact in

Electrical and Electronic Engineering top 2%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Silicon and Solar Cell Technologies
- Thin-Film Transistor Technologies
Biomedical Engineering top 10%
- Nanowire Synthesis and Applications

Papers in

Electrical and Electronic Engineering 21
- Advancements in Semiconductor Devices and Circuit Design 18
- Semiconductor materials and devices 15
- Silicon Carbide Semiconductor Technologies 7
- Integrated Circuits and Semiconductor Failure Analysis 3
- Silicon and Solar Cell Technologies 3
Biomedical Engineering 7
- Nanowire Synthesis and Applications 5

Co-authors: L. Shifren (9 shared papers)Borna J. Obradovic (7 shared papers)R. Kotlyar (10 shared papers)Tahir Ghani (6 shared papers)Anand Murthy (3 shared papers)Kajal Mistry (4 shared papers)Chris Auth (4 shared papers)M. A. Armstrong (3 shared papers)
Journals: Applied Physics Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)Journal of Computational Electronics (2 papers)IEEE Electron Device Letters (1 paper)IEEE Transactions on Nanotechnology (1 paper)
Partner nations: United States United Kingdom

In The Last Decade

S. Cea

23 papers receiving 1.6k citations

S. Cea's Hit Papers

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A 90-nm logic technology featuring strained-silicon 2004 · 514 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2004 IEEE Transactions on Electron Devices

Peers

Countries citing papers authored by S. Cea

Since Specialization

Citations

This map shows the geographic impact of S. Cea's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Cea with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Cea more than expected).

Fields of papers citing papers by S. Cea

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Cea. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Cea. The network helps show where S. Cea may publish in the future.

Co-authors

The 25 scholars most cited alongside S. Cea, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S. Cea Line = papers co-authored together S. Cea links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 25 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 90-nm logic technology featuring strained-silicon IEEE Transactions on Electron Devices ·Scott E. Thompson, M. A. Armstrong, Chris Auth, M. Alavi, Markus J. Buehler, Robert S. Chau, S. Cea, Tahir Ghani Hit paper breakdown →	2004	514
2	A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters ·Scott E. Thompson, M. A. Armstrong, Chris Auth, S. Cea, Robert S. Chau, G. Glass, T. Hoffman, J. W. Klaus	2004	415
3	A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell Scott E. Thompson, N. Anand, M. A. Armstrong, Chris Auth, B. Arcot, M. Alavi, Jeff Bielefeld, Robert M. Bigwood	2003	185
4	Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers IEEE Transactions on Electron Devices ·E.X. Wang, Philippe Matagne, L. Shifren, Borna J. Obradovic, R. Kotlyar, S. Cea, Mark A. Stettler, M.D. Giles	2006	120
5	Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology Kajal Mistry, M. A. Armstrong, Chris Auth, S. Cea, Tom Coan, Tahir Ghani, Thomas Hoffmann, Anand Murthy	2004	120
6	Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors Applied Physics Letters ·R. Kotlyar, Uygar E. Avci, S. Cea, R.A. Rios, T. Linton, Kelin J. Kuhn, Ian A. Young	2013	82
7	High performance Hi-K + metal gate strain enhanced transistors on (110) silicon Paul A. Packan, S. Cea, H. Deshpande, Tahir Ghani, M.D. Giles, Oleg Golonzka, M. Hattendorf, R. Kotlyar	2008	48
8	Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress Applied Physics Letters ·L. Shifren, X. Wang, Philippe Matagne, Borna J. Obradovic, Chris Auth, S. Cea, Tahir Ghani, Jianli He	2004	27
9	A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell Kelin J. Kuhn, M. Agostinelli, Sally Ahmed, S. Chambers, S. Cea, Soren K. Christensen, Paul B. Fischer, J. Gong	2003	27
10	Understanding stress enhanced performance in Intel 90nm CMOS technology M.D. Giles, M. A. Armstrong, Chris Auth, S. Cea, Tahir Ghani, Thomas Hoffmann, R. Kotlyar, Philippe Matagne	2004	25
11	Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress E. Wang, Philippe Matagne, L. Shifren, Borna J. Obradovic, R. Kotlyar, S. Cea, Jie He, Zheng Ma	2005	25
12	Modeling the effects of applied stress and wafer orientation in silicon devices: from long channel mobility physics to short channel performance Journal of Computational Electronics ·R. Kotlyar, M.D. Giles, S. Cea, T. Linton, L. Shifren, Cory E. Weber, Mark A. Stettler	2009	9
13	State-of-the-art TCAD: 25 years ago and today Mark A. Stettler, S. Cea, Sayed Hasan, Lei Jiang, Ananth P. Kaushik, Patrick H. Keys, R. Kotlyar, Colin Landon	2019	8
14	Modeling of ultrahighly doped shallow junctions for aggressively scaled CMOS Harold W. Kennel, S. Cea, A. D. Lilak, Patrick H. Keys, M.D. Giles, Jeong‐Mo Hwang, J. Sandford, Sean F. Corcoran	2003	7
15	Effect of band warping and wafer orientation on NMOS mobility under arbitrary applied stress Journal of Computational Electronics ·R. Kotlyar, Cory E. Weber, L. Shifren, S. Cea, M.D. Giles, Mark A. Stettler	2007	6
16	Atomistic Tight-Binding Study of Contact Resistivity in Si/SiGe PMOS Schottky Contacts IEEE Transactions on Nanotechnology ·Prasad S. Sarangapani, Cory E. Weber, Jiwon Chang, S. Cea, Michael Povolotskyi, Gerhard Klimeck, Tillmann Kubis	2018	6
17	Multidimensional Nonlinear Viscoelastic Oxidation Modeling S. Cea, Mark E. Law	1995	4
18	Strain Modeling in Advanced MOSFET Devices ECS Transactions ·S. Cea, Tahir Ghani, M.D. Giles, R. Kotlyar, Philippe Matagne, Kaizad R. Mistry, Borna J. Obradovic, Reaz Shaheed	2006	3
19	Viscoelastic Modeling of Titanium Silicidation S. Cea, Mark E. Law	1995	3
20	TCAD for logic technology process development S. Cea, S. Berrada, Kasturi Ghosh, Sayed Hasan, Patrick H. Keys, R. Mehandru, Borna J. Obradovic, Vishal A. Tiwari	2021	2

About S. Cea

S. Cea is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Hardware and Architecture, Atomic and Molecular Physics, and Optics and Computer Graphics and Computer-Aided Design, having authored 25 papers that have together received 1.6k indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (18 papers), Semiconductor materials and devices (15 papers), Silicon Carbide Semiconductor Technologies (7 papers), Nanowire Synthesis and Applications (5 papers), Semiconductor materials and interfaces (3 papers), Integrated Circuits and Semiconductor Failure Analysis (3 papers), Silicon and Solar Cell Technologies (3 papers) and VLSI and Analog Circuit Testing (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.5k citations), Biomedical Engineering (443 citations), Structural Biology (14 citations), Atomic and Molecular Physics, and Optics (229 citations) and Hardware and Architecture (38 citations). S. Cea has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include L. Shifren, Borna J. Obradovic, R. Kotlyar, Tahir Ghani, Anand Murthy, Kajal Mistry, Chris Auth, M. A. Armstrong, Scott E. Thompson and Mark T. Bohr. Their work appears in journals such as Applied Physics Letters, IEEE Transactions on Electron Devices, Journal of Computational Electronics, IEEE Electron Device Letters and IEEE Transactions on Nanotechnology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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S. Cea's Hit Papers

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