Anand Murthy

3.8k citations

18 papers · 2.9k · 1 hit paper · h-index 17

Impact in

Electrical and Electronic Engineering top 1%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
Hardware and Architecture top 5%

Papers in

Electrical and Electronic Engineering 17
- Semiconductor materials and devices 16
- Advancements in Semiconductor Devices and Circuit Design 16
- Integrated Circuits and Semiconductor Failure Analysis 5
- Silicon Carbide Semiconductor Technologies 3
- Ferroelectric and Negative Capacitance Devices 2
- 3D IC and TSV technologies 1
- Radio Frequency Integrated Circuit Design 1
Biomedical Engineering 5
- Nanowire Synthesis and Applications 5

Co-authors: Robert S. Chau (6 shared papers)J. Kavalieros (6 shared papers)Tahir Ghani (4 shared papers)Mark Doczy (4 shared papers)M. A. Armstrong (3 shared papers)Scott E. Thompson (3 shared papers)Chris Auth (3 shared papers)Mark T. Bohr (3 shared papers)
Journals: IEEE Electron Device Letters (2 papers)IEEE Transactions on Electron Devices (1 paper)SAE technical papers on CD-ROM/SAE technical paper series (1 paper)ECS Transactions (1 paper)
Partner nations: United States United Kingdom India

In The Last Decade

Anand Murthy

18 papers receiving 2.8k citations

Anand Murthy's Hit Papers

align trajectories log scale

A 90-nm logic technology featuring strained-silicon 2004 · 514 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2004 IEEE Transactions on Electron Devices

Peers

Countries citing papers authored by Anand Murthy

Since Specialization

Citations

This map shows the geographic impact of Anand Murthy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anand Murthy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anand Murthy more than expected).

Fields of papers citing papers by Anand Murthy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Anand Murthy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anand Murthy. The network helps show where Anand Murthy may publish in the future.

Co-authors

The 25 scholars most cited alongside Anand Murthy, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Anand Murthy Line = papers co-authored together Anand Murthy links everyone, so they are left out of the graph.

All Works

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18 of 18 papers shown

#	Work
1	A 90-nm logic technology featuring strained-silicon IEEE Transactions on Electron Devices ·Scott E. Thompson, M. A. Armstrong, Chris Auth, M. Alavi, Markus J. Buehler, Robert S. Chau, S. Cea, Tahir Ghani Hit paper breakdown →	2004	514
2	A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters ·Scott E. Thompson, M. A. Armstrong, Chris Auth, S. Cea, Robert S. Chau, G. Glass, T. Hoffman, J. W. Klaus	2004	415
3	A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors Tahir Ghani, M. A. Armstrong, Chris Auth, M. C. Bost, Peter K. Charvat, G. Glass, Thomas Hoffmann, Kevin B. Johnson	2004	414
4	High performance fully-depleted tri-gate CMOS transistors IEEE Electron Device Letters ·B.S. Doyle, Suman Datta, Mark Doczy, Scott A. Hareland, Ben Jin, J. Kavalieros, T. Linton, Anand Murthy	2003	342
5	A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell Chris Auth, S. Balakrishnan, M. C. Bost, R. Brain, Vinay Chikarmane, R. Heussner, M. Hussein, Jeong-Hyun Hwang	2005	190
6	A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell Scott E. Thompson, N. Anand, M. A. Armstrong, Chris Auth, B. Arcot, M. Alavi, Jeff Bielefeld, Robert M. Bigwood	2003	185
7	High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors Paul A. Packan, Sheikh Ali Akbar, M. A. Armstrong, D. Bergstrom, Mark Brazier, H. Deshpande, Kapil Dev, G. Ding	2009	152
8	A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array S. Natarajan, M. A. Armstrong, M. C. Bost, R. Brain, Mark Brazier, Chip-Hong Chang, Vinay Chikarmane, M. J. Childs	2008	147
9	Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology Kajal Mistry, M. A. Armstrong, Chris Auth, S. Cea, Tom Coan, Tahir Ghani, Thomas Hoffmann, Anand Murthy	2004	120
10	30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays Robert S. Chau, J. Kavalieros, Brian E. Roberds, Richard E. Schenker, D. Lionberger, Douglas W. Barlage, Barry M. Doyle, Reza Arghavani	2002	88
11	A 50 nm depleted-substrate CMOS transistor (DST) Robert S. Chau, J. Kavalieros, Barry M. Doyle, Anand Murthy, N. Paulsen, D. Lionberger, Douglas W. Barlage, Reza Arghavani	2002	78
12	(Invited) Past, Present and Future: SiGe and CMOS Transistor Scaling ECS Transactions ·Kelin J. Kuhn, Anand Murthy, R. Kotlyar, Markus Kühn	2010	69
13	Advanced Depleted-Substrate Transistors: Single-gate, Double-gate and Tri-gate Robert S. Chau, B.S. Doyle, J. Kavalieros, Doug William Barlage, Anand Murthy, Mark Doczy, Reza Arghavani, Suman Datta	2002	56
14	High performance Hi-K + metal gate strain enhanced transistors on (110) silicon Paul A. Packan, S. Cea, H. Deshpande, Tahir Ghani, M.D. Giles, Oleg Golonzka, M. Hattendorf, R. Kotlyar	2008	48
15	Gate-All-Around Strained Si 0.4 Ge 0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application Ankur Agrawal, Siddharth Chouksey, Willy Rachmady, Suresh Vishwanath, Srabantika Ghose, M. Mehta, Jessica M. Torres, Adedapo A. Oni	2020	43
16	High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics Douglas W. Barlage, Reza Arghavani, Gilbert Dewey, Mark Doczy, Barry M. Doyle, J. Kavalieros, Anand Murthy, Brian E. Roberds	2002	33
17	A 90 nm communication technology featuring SiGe HBT transistors, RF CMOS, precision R-L-C RF elements and 1 μm/sup 2/ 6-T SRAM cell Kelin J. Kuhn, M. Agostinelli, Sally Ahmed, S. Chambers, S. Cea, Soren K. Christensen, Paul B. Fischer, J. Gong	2003	27
18	Improvement in Noise Transmission Across Firewall of a Passenger Car SAE technical papers on CD-ROM/SAE technical paper series ·Smita Shivle, Anand Murthy	2010	3

About Anand Murthy

Anand Murthy is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Hardware and Architecture, Civil and Structural Engineering and Control and Systems Engineering, having authored 18 papers that have together received 2.9k indexed citations. Recurring topics across this work include Semiconductor materials and devices (16 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Integrated Circuits and Semiconductor Failure Analysis (5 papers), Nanowire Synthesis and Applications (5 papers), Silicon Carbide Semiconductor Technologies (3 papers), Ferroelectric and Negative Capacitance Devices (2 papers), 3D IC and TSV technologies (1 paper) and Radio Frequency Integrated Circuit Design (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (2.7k citations), Hardware and Architecture (128 citations), Biomedical Engineering (684 citations), Structural Biology (19 citations) and Atomic and Molecular Physics, and Optics (347 citations). Anand Murthy has collaborated with scholars based in United States, United Kingdom and India. Frequent co-authors include Robert S. Chau, J. Kavalieros, Tahir Ghani, Mark Doczy, M. A. Armstrong, Scott E. Thompson, Chris Auth, Mark T. Bohr, Kajal Mistry and Shwetha Sivakumar. Their work appears in journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, SAE technical papers on CD-ROM/SAE technical paper series and ECS Transactions.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Anand Murthy's Hit Papers

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