Gilbert Dewey

2.4k citations

32 papers · 2.0k · h-index 22

Impact in

Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
Atomic and Molecular Physics, and Optics top 10%
- Semiconductor Quantum Structures and Devices
- Semiconductor materials and interfaces

Papers in

Electrical and Electronic Engineering 32
- Semiconductor materials and devices 31
- Advancements in Semiconductor Devices and Circuit Design 27
- Integrated Circuits and Semiconductor Failure Analysis 6
- Ferroelectric and Negative Capacitance Devices 5
- 3D IC and TSV technologies 2
Biomedical Engineering 11
- Nanowire Synthesis and Applications 11

Co-authors: Robert S. Chau (20 shared papers)M. Radosavljević (19 shared papers)J. Kavalieros (17 shared papers)M. Metz (14 shared papers)Willy Rachmady (9 shared papers)B. Chu-Kung (9 shared papers)R. Pillarisetty (9 shared papers)Niloy Mukherjee (9 shared papers)
Journals: IEEE Electron Device Letters (2 papers)Microelectronic Engineering (1 paper)ORCA Online Research @Cardiff (Cardiff University) (1 paper)
Partner nations: United States United Kingdom

In The Last Decade

Gilbert Dewey

32 papers receiving 2.0k citations

Peers

Countries citing papers authored by Gilbert Dewey

Since Specialization

Citations

This map shows the geographic impact of Gilbert Dewey's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Gilbert Dewey with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Gilbert Dewey more than expected).

Fields of papers citing papers by Gilbert Dewey

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Gilbert Dewey. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Gilbert Dewey. The network helps show where Gilbert Dewey may publish in the future.

Co-authors

The 25 scholars most cited alongside Gilbert Dewey, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Gilbert Dewey Line = papers co-authored together Gilbert Dewey links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 32 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing Gilbert Dewey, B. Chu-Kung, J. Boardman, Joel M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu, Dmitri Lubyshev	2011	294
2	Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering J. Kavalieros, Barry M. Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, D. Lionberger, M. Metz	2006	188
3	Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation M. Radosavljević, Gilbert Dewey, Dipanjan Basu, J. Boardman, B. Chu-Kung, Joel M. Fastenau, Sanaz Kabehie, J. Kavalieros	2011	120
4	BTI reliability of 45 nm high-K + metal-gate process technology Sangwoo Pae, M. Agostinelli, Mark Brazier, Robert S. Chau, Gilbert Dewey, Tahir Ghani, M. Hattendorf, Jeffrey Hicks	2008	120
5	Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology Microelectronic Engineering ·Robert S. Chau, J.K. Brask, Suman Datta, Gilbert Dewey, Mark Doczy, B.S. Doyle, J. Kavalieros, Ben Jin	2005	116
6	Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications M. Radosavljević, B. Chu-Kung, Sean F. Corcoran, Gilbert Dewey, Mantu Kumar Hudait, Joel M. Fastenau, J. Kavalieros, W. K. Liu	2009	114
7	3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling ChingYao Huang, Gilbert Dewey, Ehren Mannebach, A. Phan, P. Morrow, Willy Rachmady, I‐Cheng Tung, Nicole K. Thomas	2020	92
8	30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays Robert S. Chau, J. Kavalieros, Brian E. Roberds, Richard E. Schenker, D. Lionberger, Douglas W. Barlage, Barry M. Doyle, Reza Arghavani	2002	88
9	High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture R. Pillarisetty, B. Chu-Kung, Sean F. Corcoran, Gilbert Dewey, J. Kavalieros, Harold W. Kennel, R. Kotlyar, Hung V. Le	2010	85
10	High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications ORCA Online Research @Cardiff (Cardiff University) ·M. Radosavljević, Tim Ashley, A. D. Andreev, S. D. Coomber, Gilbert Dewey, M. T. Emeny, M. Fearn, D.G. Hayes	2008	85
11	Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications M. Radosavljević, Gilbert Dewey, Joel M. Fastenau, J. Kavalieros, R. Kotlyar, B. Chu-Kung, W. K. Liu, Dmitri Lubyshev	2010	81
12	Ultrahigh-Speed 0.5 V Supply Voltage $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ Quantum-Well Transistors on Silicon Substrate IEEE Electron Device Letters ·Suman Datta, Gilbert Dewey, Joel M. Fastenau, Mantu Kumar Hudait, Dmitri Loubychev, W.K. Liu, M. Radosavljević, Willy Rachmady	2007	75
13	High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack Suman Datta, Gilbert Dewey, Mark Doczy, B.S. Doyle, Ben Jin, J. Kavalieros, R. Kotlyar, M. Metz	2004	69
14	300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications Willy Rachmady, Ankur Kumar Agrawal, Seung-Hun Sung, Gilbert Dewey, Siddharth Chouksey, B. Chu-Kung, Giselle Elbaz, Paul B. Fischer	2019	68
15	Heterogeneous integration of enhancement mode in 0.7 ga 0.3 as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications Mantu Kumar Hudait, Gilbert Dewey, Suman Datta, Joel M. Fastenau, J. Kavalieros, W.K. Liu, Dmitri Lubyshev, R. Pillarisetty	2007	62
16	Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications IEEE Electron Device Letters ·Gilbert Dewey, Mantu Kumar Hudait, Kangho Lee, R. Pillarisetty, Willy Rachmady, M. Radosavljević, Titash Rakshit, Robert S. Chau	2008	58
17	III–V field effect transistors for future ultra-low power applications Gilbert Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, Niloy Mukherjee, M. Radosavljević	2012	43
18	Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET Uygar E. Avci, B. Chu-Kung, Ashish Kumar Agrawal, Gilbert Dewey, Hung V. Le, Rafael Rios, Daniel H. Morris, Sayed Hasan	2015	36
19	High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics Douglas W. Barlage, Reza Arghavani, Gilbert Dewey, Mark Doczy, Barry M. Doyle, J. Kavalieros, Anand Murthy, Brian E. Roberds	2002	33
20	MOVPE III–V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications Niloy Mukherjee, J. Boardman, B. Chu-Kung, Gilbert Dewey, A. Eisenbach, Joel M. Fastenau, J. Kavalieros, W. K. Liu	2011	25

About Gilbert Dewey

Gilbert Dewey is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Electronic, Optical and Magnetic Materials, Atomic and Molecular Physics, and Optics and Condensed Matter Physics, having authored 32 papers that have together received 2.0k indexed citations. Recurring topics across this work include Semiconductor materials and devices (31 papers), Advancements in Semiconductor Devices and Circuit Design (27 papers), Nanowire Synthesis and Applications (11 papers), Integrated Circuits and Semiconductor Failure Analysis (6 papers), Ferroelectric and Negative Capacitance Devices (5 papers), 3D IC and TSV technologies (2 papers), Ga2O3 and related materials (2 papers) and Semiconductor Quantum Structures and Devices (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.9k citations), Atomic and Molecular Physics, and Optics (363 citations), Biomedical Engineering (485 citations), Materials Chemistry (246 citations) and Hardware and Architecture (31 citations). Gilbert Dewey has collaborated with scholars based in United States and United Kingdom. Frequent co-authors include Robert S. Chau, M. Radosavljević, J. Kavalieros, M. Metz, Willy Rachmady, B. Chu-Kung, R. Pillarisetty, Niloy Mukherjee, Joel M. Fastenau and R. Kotlyar. Their work appears in journals such as IEEE Electron Device Letters, Microelectronic Engineering and ORCA Online Research @Cardiff (Cardiff University).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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