Chris Auth

6.0k citations

31 papers · 4.7k · 4 hit papers · h-index 22

Impact in

Electrical and Electronic Engineering top 0.5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
Hardware and Architecture top 5%

Papers in

Electrical and Electronic Engineering 29
- Semiconductor materials and devices 26
- Advancements in Semiconductor Devices and Circuit Design 25
- Silicon Carbide Semiconductor Technologies 5
- Low-power high-performance VLSI design 4
- Ferroelectric and Negative Capacitance Devices 4
- Integrated Circuits and Semiconductor Failure Analysis 3
Electronic, Optical and Magnetic Materials 5
- Copper Interconnects and Reliability 5

Co-authors: J.D. Plummer (3 shared papers)Kajal Mistry (7 shared papers)Tahir Ghani (6 shared papers)M. A. Armstrong (4 shared papers)Scott E. Thompson (3 shared papers)Anand Murthy (3 shared papers)Mark T. Bohr (3 shared papers)Shwetha Sivakumar (2 shared papers)
Journals: IEEE Electron Device Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)Applied Physics Letters (1 paper)IEEE Solid-State Circuits Magazine (1 paper)
Partner nations: United States

In The Last Decade

Chris Auth

30 papers receiving 4.5k citations

Chris Auth's Hit Papers

align trajectories log scale

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors 2012 · 627 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2012 A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
2007 A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2004 IEEE Transactions on Electron Devices
1997 IEEE Electron Device Letters

Peers

Countries citing papers authored by Chris Auth

Since Specialization

Citations

This map shows the geographic impact of Chris Auth's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chris Auth with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chris Auth more than expected).

Fields of papers citing papers by Chris Auth

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chris Auth. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chris Auth. The network helps show where Chris Auth may publish in the future.

Co-authors

The 25 scholars most cited alongside Chris Auth, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Chris Auth Line = papers co-authored together Chris Auth links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 31 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging Kajal Mistry, Robert S. Chau, Changhwan Choi, G. Ding, K. Fischer, Tahir Ghani, R. Grover, Won Seok Han Hit paper breakdown →	2007	649
2	A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors Chris Auth, Cifford Allen, A. Blattner, D. Bergstrom, Mark Brazier, M. C. Bost, Markus J. Buehler, Vinay Chikarmane Hit paper breakdown →	2012	627
3	A 90-nm logic technology featuring strained-silicon IEEE Transactions on Electron Devices ·Scott E. Thompson, M. A. Armstrong, Chris Auth, M. Alavi, Markus J. Buehler, Robert S. Chau, S. Cea, Tahir Ghani Hit paper breakdown →	2004	514
4	Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's IEEE Electron Device Letters ·Chris Auth, J.D. Plummer Hit paper breakdown →	1997	451
5	A Logic Nanotechnology Featuring Strained-Silicon IEEE Electron Device Letters ·Scott E. Thompson, M. A. Armstrong, Chris Auth, S. Cea, Robert S. Chau, G. Glass, T. Hoffman, J. W. Klaus	2004	415
6	A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors Tahir Ghani, M. A. Armstrong, Chris Auth, M. C. Bost, Peter K. Charvat, G. Glass, Thomas Hoffmann, Kevin B. Johnson	2004	414
7	A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects Chris Auth, A. Aliyarukunju, M. Asoro, D. Bergstrom, Vinay Bhagwat, Jacquelyn Birdsall, Nabhendra Bisnik, Markus J. Buehler	2017	311
8	A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell Chris Auth, S. Balakrishnan, M. C. Bost, R. Brain, Vinay Chikarmane, R. Heussner, M. Hussein, Jeong-Hyun Hwang	2005	190
9	A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell Scott E. Thompson, N. Anand, M. A. Armstrong, Chris Auth, B. Arcot, M. Alavi, Jeff Bielefeld, Robert M. Bigwood	2003	185
10	45nm High-k + metal gate strain-enhanced transistors Chris Auth, A. Cappellani, Jang‐Soo Chun, Adam Dalis, Alexander L. Davis, Tahir Ghani, G. Glass, Timothy E. Glassman	2008	157
11	Intrinsic transistor reliability improvements from 22nm tri-gate technology S. Ramey, A. Ashutosh, Chris Auth, Jason Clifford, M. Hattendorf, Jeffrey Hicks, R. James, Anisur Rahman	2013	149
12	Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology Kajal Mistry, M. A. Armstrong, Chris Auth, S. Cea, Tom Coan, Tahir Ghani, Thomas Hoffmann, Anand Murthy	2004	120
13	Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C. Prasad, Lei Jiang, D. Singh, M. Agostinelli, Chris Auth, Travis M. Eiles, Jeffrey Hicks, C. -H. Jan	2013	76
14	22-nm fully-depleted tri-gate CMOS transistors Chris Auth	2012	66
15	A simple model for threshold voltage of surrounding-gate MOSFET's IEEE Transactions on Electron Devices ·Chris Auth, J.D. Plummer	1998	65
16	Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology Flavio Griggio, J. Palmer, Fuxiang Pan, Nikholas G. Toledo, Anthony Schmitz, Ilan Tsameret, Rahim Kasim, Gerald S. Leatherman	2018	51
17	An advanced low power, high performance, strained channel 65nm technology S. Tyagi, C. Kenyon, S.-H. Lee, N. Lindert, Miao Liu, Ramune Nagisetty, S. Natarajan, Chelsie M. Parker	2005	45
18	Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C. Prasad, M. Agostinelli, Jeffrey Hicks, S. Ramey, Chris Auth, Kajal Mistry, S. Natarajan, Paul A. Packan	2014	37
19	45nm high-k + metal gate strain-enhanced CMOS transistors Chris Auth	2008	37
20	Interconnect Stack using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing Andrew Yeoh, Advait Madhavan, Nicholas J. Kybert, Srinivasan Anand, Jung H. Shin, M. Asoro, S. Samarajeewa, Joseph M. Steigerwald	2018	33

About Chris Auth

Chris Auth is a scholar working on Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Biomedical Engineering, Hardware and Architecture and Insect Science, having authored 31 papers that have together received 4.7k indexed citations. Recurring topics across this work include Semiconductor materials and devices (26 papers), Advancements in Semiconductor Devices and Circuit Design (25 papers), Nanowire Synthesis and Applications (6 papers), Copper Interconnects and Reliability (5 papers), Silicon Carbide Semiconductor Technologies (5 papers), Low-power high-performance VLSI design (4 papers), Ferroelectric and Negative Capacitance Devices (4 papers) and Integrated Circuits and Semiconductor Failure Analysis (3 papers). The work is most often cited by research in Electrical and Electronic Engineering (4.4k citations), Hardware and Architecture (232 citations), Biomedical Engineering (943 citations), Structural Biology (22 citations) and Atomic and Molecular Physics, and Optics (465 citations). Chris Auth has collaborated with scholars based in United States. Frequent co-authors include J.D. Plummer, Kajal Mistry, Tahir Ghani, M. A. Armstrong, Scott E. Thompson, Anand Murthy, Mark T. Bohr, Shwetha Sivakumar, G. Glass and Brian L. McIntyre. Their work appears in journals such as IEEE Electron Device Letters, IEEE Transactions on Electron Devices, Applied Physics Letters and IEEE Solid-State Circuits Magazine.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Chris Auth's Hit Papers

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About Chris Auth

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