S. Biesemans

4.6k citations

244 papers · 3.7k · h-index 29

Impact in

Electrical and Electronic Engineering top 1%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- 3D IC and TSV technologies
- Low-power high-performance VLSI design
- Advancements in Photolithography Techniques
- Radio Frequency Integrated Circuit Design
Atomic and Molecular Physics, and Optics top 5%
- Quantum and electron transport phenomena
- Semiconductor materials and interfaces

Papers in

Electrical and Electronic Engineering 233
- Advancements in Semiconductor Devices and Circuit Design 156
- Semiconductor materials and devices 110
- Advancements in Photolithography Techniques 22
- Low-power high-performance VLSI design 14
- 3D IC and TSV technologies 9
Atomic and Molecular Physics, and Optics 35
- Semiconductor materials and interfaces 29
- Quantum and electron transport phenomena 6

Co-authors: Nadine Collaert (42 shared papers)Małgorzata Jurczak (61 shared papers)Sven Rogge (11 shared papers)Thomas Hoffmann (50 shared papers)G. P. Lansbergen (10 shared papers)Jacob Caro (4 shared papers)Kristin De Meyer (49 shared papers)Anabela Veloso (31 shared papers)
Journals: IEEE Electron Device Letters (25 papers)Solid-State Electronics (7 papers)Applied Physics Letters (7 papers)Microelectronic Engineering (6 papers)IEEE Transactions on Electron Devices (5 papers)
Partner nations: Belgium United States Japan

In The Last Decade

S. Biesemans

230 papers receiving 3.6k citations

Peers

Countries citing papers authored by S. Biesemans

Since Specialization

Citations

This map shows the geographic impact of S. Biesemans's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S. Biesemans with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S. Biesemans more than expected).

Fields of papers citing papers by S. Biesemans

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S. Biesemans. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S. Biesemans. The network helps show where S. Biesemans may publish in the future.

Co-authors

The 25 scholars most cited alongside S. Biesemans, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with S. Biesemans Line = papers co-authored together S. Biesemans links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Showing the 20 most-cited of 244 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET Nature Physics ·G. P. Lansbergen, Rajib Rahman, Cameron J. Wellard, Insoo Woo, Jacob Caro, Nadine Collaert, S. Biesemans, Gerhard Klimeck	2008	260
2	Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire Physical Review Letters ·H. Sellier, G. P. Lansbergen, Jacob Caro, Sven Rogge, Nadine Collaert, I. Ferain, M. Jurczak, S. Biesemans	2006	209
3	Review of FINFET technology Proceedings - IEEE International SOI Conference/Proceedings ·Małgorzata Jurczak, Nadine Collaert, Anabela Veloso, Thomas Hoffmann, S. Biesemans	2009	128
4	3D stacked IC demonstration using a through Silicon Via First approach Technical digest - International Electron Devices Meeting/Technical digest ·Jan Van Olmen, Abdelkarim Mercha, Guruprasad Katti, Cedric Huyghebaert, J. Van Aelst, Silvia Armini, Jan Vaes, Ricardo Cotrin Teixeira	2008	117
5	Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Solid-State Electronics ·T. Chiarella, Liesbeth Johanna Witters, Abdelkarim Mercha, Christoph Kerner, Michał Rakowski, Claude Ortolland, Bertrand Parvais, A. De Keersgieter	2010	107
6	Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance Technical digest - International Electron Devices Meeting/Technical digest ·Abdelkarim Mercha, Geert Van der Plas, Victor Moroz, Ingrid De Wolf, Panagiotis Asimakopoulos, Nikolaos Minas, Shinichi Domae, Dan Perry	2010	105
7	Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips Technical digest - International Electron Devices Meeting/Technical digest ·Srikanth B. Samavedam, Julien Ryckaert, Eric Beyne, Kurt G. Ronse, Naoto Horiguchi, Zsolt Tökei, Iuliana P. Radu, M. Garcia Bardon	2020	95
8	Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography IEEE Symposium on VLSI Technology ·M.J.H. van Dal, Nadine Collaert, Gerben Doornbos, Georgios Vellianitis, Gilberto Curatola, Bartek J. Pawlak, Ray Duffy, C. Jonville	2007	67
9	3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding Technical digest - International Electron Devices Meeting/Technical digest ·Guruprasad Katti, Jan Van Olmen, Cedric Huyghebaert, Anne Jourdain, Michele Stucchi, Michał Rakowski, Ingrid Debusschere, Ph. Soussan	2009	62
10	Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates IEEE Electron Device Letters ·J. A. Kittl, Małgorzata Pawlak, A. Lauwers, Caroline Demeurisse, Karl Opsomer, K.G. Anil, Christa Vrancken, M.J.H. van Dal	2005	59
11	Composition influence on the physical and electrical properties of SrxTi1−xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes Journal of Applied Physics ·N. Menou, Mihaela Ioana Popovici, Sergiu Clima, Karl Opsomer, W. Polspoel, B. Kaczer, Geert Rampelberg, Kazuyuki Tomida	2009	55
12	Multi-gate devices for the 32nm technology node and beyond European Solid-State Device Research Conference ·Nadine Collaert, A. De Keersgieter, Abhisek Dixit, Isabelle Pauline Ferain, D. Lenoble, Abdelkarim Mercha, Axel Nackaerts, Bartek J. Pawlak	2007	52
13	Wide $V_{\rm fb}$ and $V_{\rm th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics IEEE Electron Device Letters ·X.P. Wang, H.Y. Yu, mujun Li, Chunxiang Zhu, S. Biesemans, Albert Chin, Yichuang Sun, Yuan Ping Feng	2007	51
14	Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization Technical digest - International Electron Devices Meeting/Technical digest ·Lars-Åke Ragnarsson, Z. Li, Joshua Tseng, Tom Schram, Erika Rohr, M. J. Cho, Thomas Kauerauf, Thierry S. Conard	2009	49
15	Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Hans W. Mertens, Maryam Hosseini, T. Chiarella, D. L. Zhou, Shengyung Wang, Geert Mannaert, Emmanuel Dupuy, D. Radisic	2023	48
16	A 0.13 μm CMOS platform with Cu/low-k interconnects for system on chip applications Symposium on VLSI Technology ·T. Schiml, S. Biesemans, G. Brase, Lloyd G. Burrell, Adam Cowley, K.C. Chen, Andreas von Ehrenwall, Birgit von Ehrenwall	2002	47
17	Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL Symposium on VLSI Technology ·Nadine Collaert, R. Rooyackers, Francesca Clemente, Ian Cayrefourcq, Bruno Ghyselen, K. Tamer San, B. Eyckens, Małgorzata Jurczak	2006	46
18	Multi-gate devices for the 32nm technology node and beyond Solid-State Electronics ·Nadine Collaert, A. De Keersgieter, Abhisek Dixit, Isabelle Pauline Ferain, D. Lenoble, Abdelkarim Mercha, Axel Nackaerts, Bartek J. Pawlak	2008	46
19	Performance improvement of tall triple gate devices with strained SiN layers IEEE Electron Device Letters ·Nadine Collaert, A. De Keersgieter, K.G. Anil, R. Rooyackers, Geert Eneman, M. W. Goodwin, B. Eyckens, Erik Sleeckx	2005	43
20	Tall triple-gate devices with TiN/HfO/sub 2/ gate stack Symposium on VLSI Technology ·Nadine Collaert, Marc Demand, Isabelle Pauline Ferain, J. G. Lisoni, Raghunath Singanamalla, Paul Zimmerman, Tom Schram, Geert Mannaert	2005	41

About S. Biesemans

S. Biesemans is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Electronic, Optical and Magnetic Materials, Condensed Matter Physics and Mechanical Engineering, having authored 244 papers that have together received 3.7k indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (156 papers), Semiconductor materials and devices (110 papers), Semiconductor materials and interfaces (29 papers), Advancements in Photolithography Techniques (22 papers), Low-power high-performance VLSI design (14 papers), 3D IC and TSV technologies (9 papers), Copper Interconnects and Reliability (7 papers) and Quantum and electron transport phenomena (6 papers). The work is most often cited by research in Electrical and Electronic Engineering (3.1k citations), Atomic and Molecular Physics, and Optics (759 citations), Hardware and Architecture (77 citations), Structural Biology (7 citations) and Biomedical Engineering (113 citations). S. Biesemans has collaborated with scholars based in Belgium, United States and Japan. Frequent co-authors include Nadine Collaert, Małgorzata Jurczak, Sven Rogge, Thomas Hoffmann, G. P. Lansbergen, Jacob Caro, Kristin De Meyer, Anabela Veloso, Philippe P. Absil and R. Rooyackers. Their work appears in journals such as IEEE Electron Device Letters, Solid-State Electronics, Applied Physics Letters, Microelectronic Engineering and IEEE Transactions on Electron Devices.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

S. Biesemans

Impact in

Papers in i

In The Last Decade

S. Biesemans

Peers

Countries citing papers authored by S. Biesemans

Fields of papers citing papers by S. Biesemans

All Works

About S. Biesemans

Explore authors with similar magnitude of impact

Papers in