A. Chou

1.3k citations

24 papers · 724 · h-index 11

Impact in

Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Radio Frequency Integrated Circuit Design
- Ferroelectric and Negative Capacitance Devices
Atomic and Molecular Physics, and Optics

Papers in

Electrical and Electronic Engineering 23
- Semiconductor materials and devices 23
- Advancements in Semiconductor Devices and Circuit Design 21
- Integrated Circuits and Semiconductor Failure Analysis 11
- Ferroelectric and Negative Capacitance Devices 6
- Advanced Memory and Neural Computing 2
- Silicon Carbide Semiconductor Technologies 1
Condensed Matter Physics 1
- GaN-based semiconductor devices and materials 1

Co-authors: Min Yang (3 shared papers)J. H. Stathis (3 shared papers)K. Chan (2 shared papers)M. Ieong (3 shared papers)Kafai Lai (2 shared papers)G. Freeman (3 shared papers)S. Springer (2 shared papers)L. Wagner (2 shared papers)
Journals: Applied Physics Letters (6 papers)IEEE Electron Device Letters (2 papers)IBM Journal of Research and Development (1 paper)Microelectronic Engineering (1 paper)IEEE Transactions on Electron Devices (1 paper)
Partner nations: United States United Kingdom Taiwan

In The Last Decade

A. Chou

23 papers receiving 690 citations

Peers

Countries citing papers authored by A. Chou

Since Specialization

Citations

This map shows the geographic impact of A. Chou's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Chou with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Chou more than expected).

Fields of papers citing papers by A. Chou

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Chou. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Chou. The network helps show where A. Chou may publish in the future.

Co-authors

The 25 scholars most cited alongside A. Chou, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with A. Chou Line = papers co-authored together A. Chou links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 24 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Record RF performance of 45-nm SOI CMOS Technology Sungjae Lee, B. Jagannathan, Shreesh Narasimha, A. Chou, N. Zamdmer, Jim Johnson, R. Williams, L. Wagner, Jonghae Kim, Jean‐Olivier Plouchart, John J. Pekarik, S. Springer, G. Freeman	2007	145
2	Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO₂ gate dielectrics IEEE Electron Device Letters ·Min Yang, E. P. Gusev, M. Ieong, Oleg Gluschenkov, D. Boyd, K. Chan, P. Kozlowski, C. D’Emic, R.M. Sicina, P. Jamison, A. Chou	2003	135
3	Hybrid-orientation technology (HOT): opportunities and challenges IEEE Transactions on Electron Devices ·Min Yang, V. Chan, K. Chan, L. Shi, David Fried, J. H. Stathis, A. Chou, Evgeni Gusev, J. A. Ott, Lindsay Burns, Massimo V. Fischetti, M. Ieong	2006	133
4	Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism Applied Physics Letters ·A. Chou, Kafai Lai, Kiran Kumar, Prasenjit Chowdhury, Jack C. Lee	1997	101
5	Broad energy distribution of NBTI-induced interface states in p-MOSFETs with ultra-thin nitrided oxide J. H. Stathis, G. LaRosa, A. Chou	2004	35
6	Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices Symposium on VLSI Technology ·S. Lee, R. Wachnik, P. Hyde, L. Wagner, J. Johnson, A. Chou, Arvind Kumar, Tosihide H. YOSIDA, T. Standaert, B. Greene, T. Yamashita, Karthik Balakrishnan, H. Bu, S. Springer, G. Freeman, W.K. Henson, E. Nowak	2013	30
7	Optimization of sub 3 nm gate dielectrics grown by rapid thermal oxidation in a nitric oxide ambient Applied Physics Letters ·Kiran Kumar, A. Chou, Chuan Lin, Prasenjit Choudhury, Jack C. Lee, J. Lowell	1997	27
8	Plasma damage and photo-annealing effects of thin gate oxides and oxynitrides during O₂ plasma exposure IEEE Electron Device Letters ·K. Lai, K.S. Kumar, A. Chou, J.C. Lee	1996	22
9	Reliability of gate oxide grown on nitrogen-implanted Si substrates Applied Physics Letters ·Chuan Lin, A. Chou, Prasenjit Choudhury, Jack C. Lee, Kiran Kumar, B.S. Doyle, H. Rahimpour Soleimani	1996	19
10	Improvement of ultrathin gate oxide and oxynitride integrity using fluorine implantation technique Applied Physics Letters ·Prasenjit Chowdhury, A. Chou, Kiran Kumar, (unknown), Jack C. Lee	1997	19
11	45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications IBM Journal of Research and Development ·Subramanian S. Iyer, G. Freeman, Colin J. Brodsky, A. Chou, Dan Corliss, S. Jain, N. Lustig, V. McGahay, (unknown), J. Norum, Karen Nummy, P. Parries, S. Sankaran, C. Sheraw, Pushkara R. Varanasi, G. Wang, M. Weybright, X. Yu, E.F. Crabbé, P. Agnello	2011	13
12	Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates Microelectronic Engineering ·J. H. Stathis, R. Bolam, Min Yang, Terence B. Hook, A. Chou, G. LaRosa	2005	7
13	Optimization of gate dopant concentration and microstructure for improved electrical and reliability characteristics of ultrathin oxides and N2O oxynitrides Applied Physics Letters ·A. Chou, Kafai Lai, Kiran Kumar, Jack C. Lee, Mark Gardner, J. Fulford	1996	5
14	Leverage smart system services technology for smart green building management Ko‐Yang Wang, Grace Lin, Paul B. Chou, A. Chou	2012	5
15	Plasma charging damage in SOI technology A. Mocuta, T. Hook, A. Chou, T. Wagner, A. K. Stamper, Mukesh Khare, Jeff Gambino	2002	5
16	2 ^nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond C. Ortolland, D. Jaeger, Timothy McArdle, C. DeWan, Robert R. Robison, Kai Zhao, J. Cai, P. Chang, Y. Liu, V. Varadarajan, G. Wang, A. Chou, Dimitris P. Ioannou, P. Oldiges, P. Agnello, (unknown), Vijay Narayanan, G. Freeman	2013	4
17	Effect of BF2 implantation on ultrathin gate oxide reliability Applied Physics Letters ·Chuan Lin, A. Chou, Kiran Kumar, Prasenjit Choudhury, Jack C. Lee	1996	4
18	Gate-Last I/O Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies 2021 IEEE International Electron Devices Meeting (IEDM) ·Maruf Bhuiyan, M. Kim, H. Zhou, Hansel Lo, S. Siddiqui, M. Stolfi, T. Guarini, R. Pujari, E. Davey, Erin Stuckert, J. Li, A. Chou, K. Zhao, M. Wang, Dechao Guo, B. Colombeau, N. Loubet, B. Haran, H. Bu	2021	4
19	Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications V. Ku, R.S. Amos, An Steegen, C. Cabral, (unknown), (unknown), (unknown), Y. Li, M. Gribelyuk, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Ernest Y. Wu, A. Chou, (unknown), H.C. Ng, M. Ieong, (unknown), (unknown), (unknown), Wilfried Haensch	2003	3
20	Dual gate oxide charging damage in damascene copper technologies A. K. Stamper, A. Chou, Terence B. Hook	2002	3

About A. Chou

A. Chou is a scholar working on Electrical and Electronic Engineering, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Building and Construction and Materials Chemistry, having authored 24 papers that have together received 724 indexed citations. Recurring topics across this work include Semiconductor materials and devices (23 papers), Advancements in Semiconductor Devices and Circuit Design (21 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers), Ferroelectric and Negative Capacitance Devices (6 papers), Advanced Memory and Neural Computing (2 papers), Silicon Carbide Semiconductor Technologies (1 paper), Electronic and Structural Properties of Oxides (1 paper) and GaN-based semiconductor devices and materials (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (696 citations), Atomic and Molecular Physics, and Optics (86 citations), Materials Chemistry (117 citations), Condensed Matter Physics (22 citations) and Biomedical Engineering (78 citations). A. Chou has collaborated with scholars based in United States, United Kingdom and Taiwan. Frequent co-authors include Min Yang, J. H. Stathis, K. Chan, M. Ieong, Kafai Lai, G. Freeman, S. Springer, L. Wagner, P. Kozlowski and D. Boyd. Their work appears in journals such as Applied Physics Letters, IEEE Electron Device Letters, IBM Journal of Research and Development, Microelectronic Engineering and IEEE Transactions on Electron Devices.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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