Terence B. Hook

3.9k citations

100 papers · 1.9k · 1 hit paper · h-index 25

Impact in

Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
- Advancements in Battery Materials
Hardware and Architecture top 10%

Papers in

Electrical and Electronic Engineering 99
- Semiconductor materials and devices 82
- Advancements in Semiconductor Devices and Circuit Design 81
- Integrated Circuits and Semiconductor Failure Analysis 35
- Ferroelectric and Negative Capacitance Devices 12
- Silicon Carbide Semiconductor Technologies 8
- Low-power high-performance VLSI design 8
- Electrostatic Discharge in Electronics 7
- Silicon and Solar Cell Technologies 5
Biomedical Engineering 7

Co-authors: Abhisek Dixit (12 shared papers)Isaac Lauer (3 shared papers)R. Mann (5 shared papers)Jeffrey B. Johnson (7 shared papers)Michael Guillorn (1 shared paper)Anil K. Bansal (7 shared papers)Phil Oldiges (2 shared papers)N. Rovedo (5 shared papers)
Journals: IEEE Transactions on Electron Devices (25 papers)IEEE Electron Device Letters (7 papers)Applied Physics Letters (2 papers)IEEE Journal of the Electron Devices Society (2 papers)Japanese Journal of Applied Physics (2 papers)
Partner nations: United States India Germany

In The Last Decade

Terence B. Hook

92 papers receiving 1.8k citations

Terence B. Hook's Hit Papers

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Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets 2017 · 371 citations

Peers

Countries citing papers authored by Terence B. Hook

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Citations

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Fields of papers citing papers by Terence B. Hook

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Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Terence B. Hook. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Terence B. Hook. The network helps show where Terence B. Hook may publish in the future.

Co-authors

The 25 scholars most cited alongside Terence B. Hook, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Terence B. Hook Line = papers co-authored together Terence B. Hook links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 100 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets Joule ·Terence B. Hook Hit paper breakdown →	2017	371
2	Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond Seong-Dong Kim, Michael Guillorn, Isaac Lauer, Phil Oldiges, Terence B. Hook, Myung-Hee Na	2015	123
3	Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs IEEE Transactions on Electron Devices ·Zhi Cheng Yuan, Shahriar Rizwan, Michael Wong, Kyle D. Holland, S.E. Anderson, Terence B. Hook, Diego Kienle, S.M. GadelRab, Prasad S. Gudem, Mani Vaidyanathan	2016	69
4	Lateral ion implant straggle and mask proximity effect IEEE Transactions on Electron Devices ·Terence B. Hook, J. Brown, P.E. Cottrell, E.L. Adler, D. Hoyniak, J. W. Johnson, R. Mann	2003	66
5	The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology IEEE Transactions on Electron Devices ·Terence B. Hook, E.L. Adler, F Guarin, J. Lukaitis, N. Rovedo, K. Schruefer	2001	66
6	High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering V. Chan, R. Rengarajan, N. Rovedo, Wei Jin, Terence B. Hook, P. Nguyen, Jia Chen, E. Nowak, Xiangdong Chen, D. Lea, Ashima Chakravarti, V. Ku, Shiwei Yang, An Steegen, Christopher Baiocco, Padraic Shafer, Hung Ng, Shih-Fen Huang, C. Wann	2004	63
7	Channel doping impact on FinFETs for 22nm and beyond C.-H. Lin, R. Kambhampati, Robert J. Miller, Terence B. Hook, A. Bryant, Wilfried Haensch, P. Oldiges, Isaac Lauer, T. Yamashita, V. Basker, T. Standaert, K. Rim, E. Leobandung, H. Bu, Mukesh Khare	2012	56
8	Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET IEEE Electron Device Letters ·Ramendra Singh, Kritika Aditya, Shivendra Singh Parihar, Yogesh Singh Chauhan, Reinaldo A. Vega, Terence B. Hook, Abhisek Dixit	2018	54
9	Enchanced multi-threshold (MTCMOS) circuits using variable well bias Stephen Kosonocky, M. Immediato, P.E. Cottrell, Terence B. Hook, R. Mann, Jeffrey S. Brown	2001	53
10	Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs IEEE Transactions on Electron Devices ·Ishita Jain, Anshul Gupta, Terence B. Hook, Abhisek Dixit	2018	47
11	Mechanism of Threshold Voltage Shift (ΔV_th) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs Japanese Journal of Applied Physics ·Chuan-Hsi Liu, Ming T. Lee, Chih-yung Lin, Jen-Kon Chen, Y.T. Loh, Fu‐Tai Liou, K. Schruefer, Anastasios A. Katsetos, Zhijian Yang, N. Rovedo, Terence B. Hook, C. Wann, Tze-Chiang Chen	2002	40
12	Hot-electron induced interface traps in metal/SiO2/Si capacitors: The effect of gate-induced strain Applied Physics Letters ·Terence B. Hook, T. P.	1986	39
13	Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology Y. M. Lee, M. H. Na, Ashley Chu, Adam Young, Terence B. Hook, Lars W. Liebmann, E. Nowak, Seokhyeon Baek, Rwik Sengupta, H. Trombley, Xiren Miao	2017	39
14	Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies IEEE Transactions on Electron Devices ·Xiaobin Yuan, Takashi Shimizu, U. Mahalingam, Jeffrey S. Brown, Kazi Z. Habib, D. Tekleab, Tai-Chi Su, Satadru Sarkar, C.M. Olsen, Hyun-Woo Lee, Li-Hong Pan, Terence B. Hook, Jin‐Ping Han, Jae-Eun Park, Myung-Hee Na, K. Rim	2011	38
15	The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's IEEE Transactions on Electron Devices ·T.G. Ference, Jay Burnham, William F. Clark, Terence B. Hook, S. Mittl, K. Watson, Liang-Kai Han	1999	35
16	Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics C.H. Liu, M.T. Lee, Chih‐Yung Lin, J. Chen, K. Schruefer, J. Brighten, N. Rovedo, Terence B. Hook, Mukesh Khare, Shih-Fen Huang, C. Wann, Tze-Chiang Chen, T.H. Ning	2002	35
17	Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond IEEE Electron Device Letters ·Jeffrey B. Johnson, Terence B. Hook, Yoo-Mi Lee	2008	32
18	3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes IEEE Transactions on Electron Devices ·Anil K. Bansal, Charu Gupta, Anshul Gupta, Ramendra Singh, Terence B. Hook, Abhisek Dixit	2018	32
19	Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating IEEE Transactions on Electron Devices ·Anshul Gupta, Charu Gupta, Reinaldo A. Vega, Terence B. Hook, Abhisek Dixit	2019	31
20	Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology IEEE Journal of the Electron Devices Society ·Anil K. Bansal, Ishita Jain, Terence B. Hook, Abhisek Dixit	2016	30

About Terence B. Hook

Terence B. Hook is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Hardware and Architecture, Materials Chemistry and Atomic and Molecular Physics, and Optics, having authored 100 papers that have together received 1.9k indexed citations. Recurring topics across this work include Semiconductor materials and devices (82 papers), Advancements in Semiconductor Devices and Circuit Design (81 papers), Integrated Circuits and Semiconductor Failure Analysis (35 papers), Ferroelectric and Negative Capacitance Devices (12 papers), Silicon Carbide Semiconductor Technologies (8 papers), Low-power high-performance VLSI design (8 papers), Electrostatic Discharge in Electronics (7 papers) and Silicon and Solar Cell Technologies (5 papers). The work is most often cited by research in Electrical and Electronic Engineering (1.8k citations), Hardware and Architecture (73 citations), Electronic, Optical and Magnetic Materials (121 citations), Materials Chemistry (302 citations) and Renewable Energy, Sustainability and the Environment (101 citations). Terence B. Hook has collaborated with scholars based in United States, India and Germany. Frequent co-authors include Abhisek Dixit, Isaac Lauer, R. Mann, Jeffrey B. Johnson, Michael Guillorn, Anil K. Bansal, Phil Oldiges, N. Rovedo, Seong-Dong Kim and P.E. Cottrell. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Applied Physics Letters, IEEE Journal of the Electron Devices Society and Japanese Journal of Applied Physics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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