Terence B. Hook

4.0k citations

117 papers · 3.2k · 2 hit papers · h-index 28

Impact in

Electrical and Electronic Engineering top 1%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
Hardware and Architecture top 5%

Papers in

Electrical and Electronic Engineering 116
- Semiconductor materials and devices 98
- Advancements in Semiconductor Devices and Circuit Design 94
- Integrated Circuits and Semiconductor Failure Analysis 41
- Ferroelectric and Negative Capacitance Devices 15
- Silicon Carbide Semiconductor Technologies 9
- Low-power high-performance VLSI design 8
- Electrostatic Discharge in Electronics 7
- Silicon and Solar Cell Technologies 6
Hardware and Architecture 6

Co-authors: Abhisek Dixit (12 shared papers)Isaac Lauer (3 shared papers)Randy W. Mann (5 shared papers)Jeffrey B. Johnson (7 shared papers)Nivo Rovedo (5 shared papers)Phil J. Oldiges (2 shared papers)Anil K. Bansal (7 shared papers)E.L. Adler (2 shared papers)
Journals: IEEE Transactions on Electron Devices (25 papers)IEEE Electron Device Letters (7 papers)Microelectronics Reliability (2 papers)IEEE Transactions on Device and Materials Reliability (2 papers)IEEE Journal of the Electron Devices Society (2 papers)
Partner nations: United States India Germany

In The Last Decade

Terence B. Hook

111 papers receiving 3.1k citations

Terence B. Hook's Hit Papers

align trajectories log scale

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET 2017 · 796 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2017 Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
2017 Joule

Peers

Countries citing papers authored by Terence B. Hook

Since Specialization

Citations

This map shows the geographic impact of Terence B. Hook's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Terence B. Hook with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Terence B. Hook more than expected).

Fields of papers citing papers by Terence B. Hook

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Terence B. Hook. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Terence B. Hook. The network helps show where Terence B. Hook may publish in the future.

Co-authors

The 25 scholars most cited alongside Terence B. Hook, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Terence B. Hook Line = papers co-authored together Terence B. Hook links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 117 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N. Loubet, Terence B. Hook, Pietro Montanini, Chun Wing Yeung, Siva Kanakasabapathy, M. Guillom, Tomohiro YAMASHITA, J. Zhang Hit paper breakdown →	2017	796
2	Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets Joule ·Terence B. Hook Hit paper breakdown →	2017	375
3	Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond Seong-Dong Kim, Michael Guillorn, Isaac Lauer, Phil J. Oldiges, Terence B. Hook, Myung-Hee Na	2015	125
4	A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels Ruijie Xie, Pietro Montanini, Kerem Akarvardar, Neeraj Tripathi, Bala Haran, Stephen Martin Johnson, Terence B. Hook, Bassem Hamieh	2016	116
5	A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI Kwangyou Seo, Bala Haran, Divya Gupta, Dechao Guo, Theodorus E. Standaert, Ren Xie, Huiling Shang, Emre Alptekin	2014	82
6	Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs IEEE Transactions on Electron Devices ·Zhi Cheng Yuan, Shahriar Rizwan, Michael Wong, Kyle David Holland, S.E. Anderson, Terence B. Hook, Diego Kienle, S.M. GadelRab	2016	70
7	High performance and low power transistors integrated in 65nm bulk CMOS technology Zuying Luo, An Steegen, Manfred Eller, Randy W. Mann, Christopher V. Baiocco, P. Nguyen, L. Kim, Mark Hoinkis	2005	68
8	The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology IEEE Transactions on Electron Devices ·Terence B. Hook, E.L. Adler, Fernando J. Guarin, J. Lukaitis, Nivo Rovedo, Klaus Schruefer	2001	67
9	Lateral ion implant straggle and mask proximity effect IEEE Transactions on Electron Devices ·Terence B. Hook, J. Brown, P.E. Cottrell, E.L. Adler, Dennis Hoyniak, J. W. Johnson, Randy W. Mann	2003	67
10	High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering V. Chan, Rajesh Rengarajan, Nivo Rovedo, Wei Jin, Terence B. Hook, P. Nguyen, Jia Chen, Etienne Nowak	2004	64
11	Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET IEEE Electron Device Letters ·Ramendra Singh, Kritika Aditya, Shivendra Singh Parihar, Yogesh Singh Chauhan, Reinaldo A. Vega, Terence B. Hook, Abhisek Dixit	2018	56
12	Channel doping impact on FinFETs for 22nm and beyond C.-H. Lin, R. Kambhampati, Robert J. Miller, Terence B. Hook, A. Bryant, Wilfried E. Haensch, Philip J. Oldiges, Isaac Lauer	2012	54
13	FINFET technology featuring high mobility SiGe channel for 10nm and beyond Dechao Guo, G. Karve, Gen Tsutsui, KY Lim, Robert R. Robison, Terence B. Hook, Reinaldo A. Vega, D. Liu	2016	53
14	Enchanced multi-threshold (MTCMOS) circuits using variable well bias Stephen V. Kosonocky, M. J. Immediato, P.E. Cottrell, Terence B. Hook, Randy W. Mann, Jeffrey Scott Brown	2001	50
15	Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs IEEE Transactions on Electron Devices ·Ishita Jain, Anshul Gupta, Terence B. Hook, Abhisek Dixit	2018	48
16	UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below L. Grenouillet, Maud Vinet, J. Gimbert, Bastien Giraud, Jean-Philippe Noël, Qijiong Liu, Prasanna Khare, M.-A. Jaud	2012	43
17	Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies IEEE Transactions on Electron Devices ·Xiaobin Yuan, Takashi Shimizu, U. Mahalingam, Jeffrey Scott Brown, Kazi Z. Habib, Daniel G. Tekleab, Tai-Chi Su, Satadru Sarkar	2011	40
18	Hot-electron induced interface traps in metal/SiO2/Si capacitors: The effect of gate-induced strain Applied Physics Letters ·Terence B. Hook, T. P.	1986	39
19	Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology Y. M. Lee, M. H. Na, Ashley Chu, Adam C. Young, Terence B. Hook, Lars W. Liebmann, Etienne Nowak, Seokhyeon Baek	2017	39
20	Mechanism of Threshold Voltage Shift (ΔVth) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs Japanese Journal of Applied Physics ·Chuan-Hsi Liu, Ming T. Lee, Chih-yung Lin, Jen-Kon Chen, Y.T. Loh, Fu‐Tai Liou, Klaus Schruefer, Anastasios A. Katsetos	2002	39

About Terence B. Hook

Terence B. Hook is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Electronic, Optical and Magnetic Materials, Biomedical Engineering and Atomic and Molecular Physics, and Optics, having authored 117 papers that have together received 3.2k indexed citations. Recurring topics across this work include Semiconductor materials and devices (98 papers), Advancements in Semiconductor Devices and Circuit Design (94 papers), Integrated Circuits and Semiconductor Failure Analysis (41 papers), Ferroelectric and Negative Capacitance Devices (15 papers), Silicon Carbide Semiconductor Technologies (9 papers), Low-power high-performance VLSI design (8 papers), Electrostatic Discharge in Electronics (7 papers) and Silicon and Solar Cell Technologies (6 papers). The work is most often cited by research in Electrical and Electronic Engineering (3.0k citations), Hardware and Architecture (116 citations), Biomedical Engineering (514 citations), Materials Chemistry (403 citations) and Electronic, Optical and Magnetic Materials (139 citations). Terence B. Hook has collaborated with scholars based in United States, India and Germany. Frequent co-authors include Abhisek Dixit, Isaac Lauer, Randy W. Mann, Jeffrey B. Johnson, Nivo Rovedo, Phil J. Oldiges, Anil K. Bansal, E.L. Adler, Michael Guillorn and Seong-Dong Kim. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, Microelectronics Reliability, IEEE Transactions on Device and Materials Reliability and IEEE Journal of the Electron Devices Society.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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