V. Putcha

751 citations

42 papers · 542 · h-index 13

Impact in

Condensed Matter Physics top 10%
- GaN-based semiconductor devices and materials
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Radio Frequency Integrated Circuit Design
- Advanced Memory and Neural Computing

Papers in

Electrical and Electronic Engineering 41
- Semiconductor materials and devices 38
- Advancements in Semiconductor Devices and Circuit Design 24
- Integrated Circuits and Semiconductor Failure Analysis 10
- Ferroelectric and Negative Capacitance Devices 7
- Radio Frequency Integrated Circuit Design 4
Condensed Matter Physics 14
- GaN-based semiconductor devices and materials 14

Co-authors: Nadine Collaert (26 shared papers)Bertrand Parvais (19 shared papers)D. Linten (14 shared papers)J. Franco (19 shared papers)B. Kaczer (17 shared papers)Niamh Waldron (12 shared papers)A. Alian (15 shared papers)Pieter Weckx (9 shared papers)
Journals: IEEE Transactions on Electron Devices (3 papers)IEEE Transactions on Nuclear Science (3 papers)Journal of Applied Physics (2 papers)Microelectronics Reliability (2 papers)Semiconductor Science and Technology (1 paper)
Partner nations: Belgium United States Austria

In The Last Decade

V. Putcha

41 papers receiving 525 citations

Peers

Countries citing papers authored by V. Putcha

Since Specialization

Citations

This map shows the geographic impact of V. Putcha's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Putcha with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Putcha more than expected).

Fields of papers citing papers by V. Putcha

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by V. Putcha. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Putcha. The network helps show where V. Putcha may publish in the future.

Co-authors

The 25 scholars most cited alongside V. Putcha, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with V. Putcha Line = papers co-authored together V. Putcha links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 42 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance VUBIR (Vrije Universiteit Brussel) ·Uthayasankaran Peralagu, A. Alian, V. Putcha, Ahmad Khaled, R. Rodríguez, A. Sibaja-Hernandez, Shu-Chiuan Chang, Eddy Simoen, Simeng E. Zhao, Brice De Jaeger, Daniel M. Fleetwood, Piet Wambacq, Ming Zhao, Bertrand Parvais, Niamh Waldron, Nadine Collaert	2019	61
2	A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability Microelectronics Reliability ·Ben Kaczer, J. Franco, Pieter Weckx, Ph. Roussel, V. Putcha, E. Bury, Marko Simicic, Adrian Chasin, D. Linten, Bertrand Parvais, Francky Catthoor, G. Rzepa, Michael Waltl, Tibor Grasser	2018	52
3	Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm Pieter Weckx, Julien Ryckaert, V. Putcha, A. De Keersgieter, Juergen Boemmels, P. Schuddinck, Doyoung Jang, Dmitry Yakimets, M. Garcia Bardon, L.-Å. Ragnarsson, Prasanth Raghavan, Ryunyeong Kim, A. Spessot, Diederik Verkest, A. Mocuta	2017	39
4	Statistical poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels R. Degraeve, Sergiu Clima, V. Putcha, B. Kaczer, Ph. Roussel, D. Linten, G. Groeseneken, A. Arreghini, M. Karner, C. Kernstock, Zlatan Stanojević, G. Van den bosch, Jan Van Houdt, A. Furnémont, Aaron Thean	2015	31
5	Total-Ionizing-Dose Effects and Low-Frequency Noise in 16-nm InGaAs FinFETs With HfO₂/Al₂O₃ Dielectrics IEEE Transactions on Nuclear Science ·Stefano Bonaldo, V. Putcha, Dimitri Linten, Sokrates T. Pantelides, Robert A. Reed, Ronald D. Schrimpf, Daniel M. Fleetwood, Simeng E. Zhao, Andrew O’Hara, Mariia Gorchichko, En Xia Zhang, Simone Gerardin, A. Paccagnella, Niamh Waldron, Nadine Collaert	2019	29
6	Defect profiling in FEFET Si:HfO2 layers Applied Physics Letters ·Barry O’Sullivan, V. Putcha, Roman Izmailov, V. V. Afanas’ev, Eddy Simoen, Taehwan Jung, Y. Higashi, R. Degraeve, B. Truijen, B. Kaczer, N. Ronchi, S. R. C. McMitchell, Kaustuv Banerjee, Sergiu Clima, L. Breuil, G. Van den bosch, D. Linten, Jan Van Houdt	2020	25
7	Low-Frequency Noise Investigation of GaN/AlGaN Metal–Oxide–Semiconductor High-Electron-Mobility Field-Effect Transistor With Different Gate Length and Orientation IEEE Transactions on Electron Devices ·Kenichiro Takakura, V. Putcha, Eddy Simoen, A. Alian, Uthayasankaran Peralagu, Niamh Waldron, Bertrand Parvais, Nadine Collaert	2020	24
8	GaN-on-Si mm-wave RF Devices Integrated in a 200mm CMOS Compatible 3-Level Cu BEOL Bertrand Parvais, A. Alian, Uthayasankaran Peralagu, R. Rodríguez, Sachin Yadav, Ahmad Khaled, Rana ElKashlan, V. Putcha, A. Sibaja-Hernandez, Ming Zhao, Piet Wambacq, Nadine Collaert, Niamh Waldron	2020	19
9	The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits Solid-State Electronics ·B. Kaczer, J. Franco, Pieter Weckx, Ph. Roussel, Marko Simicic, V. Putcha, E. Bury, M. Cho, R. Degraeve, D. Linten, G. Groeseneken, Peter Debacker, Bertrand Parvais, Prasanth Raghavan, Francky Catthoor, G. Rzepa, Michael Waltl, Wolfgang Goes, Tibor Grasser	2016	18
10	Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND A. Subirats, A. Arreghini, E. Capogreco, Romain Delhougne, C.-L. Tan, Andriy Hikavyy, L. Breuil, R. Degraeve, V. Putcha, G. Van den bosch, D. Linten, A. Furnémont	2017	16
11	Advanced MOSFET variability and reliability characterization array Lirias (KU Leuven) ·Marko Simicic, V. Putcha, Bertrand Parvais, Pieter Weckx, B. Kaczer, G. Groeseneken, Georges Gielen, D. Linten, A. Thean	2015	16
12	Total-Ionizing-Dose Effects on InGaAs FinFETs With Modified Gate-stack IEEE Transactions on Nuclear Science ·Simeng E. Zhao, Stefano Bonaldo, Pengfei Wang, En Xia Zhang, Niamh Waldron, Nadine Collaert, V. Putcha, Dimitri Linten, Simone Gerardin, A. Paccagnella, Ronald D. Schrimpf, Robert A. Reed, Daniel M. Fleetwood	2019	16
13	On the distribution of oxide defect levels in Al2O3 and HfO2 high-k dielectrics deposited on InGaAs metal-oxide-semiconductor devices studied by capacitance-voltage hysteresis Journal of Applied Physics ·Abhitosh Vais, J. Franco, Dennis Lin, V. Putcha, Sonja Sioncke, A. Mocuta, Nadine Collaert, Aaron Thean, K. De Meyer	2017	15
14	A New Quality Metric for III–V/High-k MOS Gate Stacks Based on the Frequency Dispersion of Accumulation Capacitance and the CET IEEE Electron Device Letters ·Abhitosh Vais, J. Franco, Koen Martens, Dennis Lin, Sonja Sioncke, V. Putcha, Laura Nyns, Jan Willem Maes, Qi Xie, Michael Givens, Fu Tang, Xiaoqiang Jiang, A. Mocuta, Nadine Collaert, Aaron Thean, K. De Meyer	2017	12
15	Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited) J. Franco, V. Putcha, Abhitosh Vais, Sonja Sioncke, Niamh Waldron, D. L. Zhou, G. Rzepa, Ph. Roussel, G. Groeseneken, Marc Heyns, Nadine Collaert, D. Linten, Tibor Grasser, B. Kaczer	2017	12
16	On the Apparent Non-Arrhenius Temperature Dependence of Charge Trapping in IIIV/High-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math> </inline-formula> MOS Stack IEEE Transactions on Electron Devices ·V. Putcha, J. Franco, Abhitosh Vais, Sonja Sioncke, B. Kaczer, Dimitri Linten, G. Groeseneken	2018	11
17	Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: Demonstration of a suitable gate stack for top and bottom tier nMOS J. Franco, Liesbeth Witters, A. Vandooren, Hiroaki Arimura, Sonja Sioncke, V. Putcha, Abhitosh Vais, Qi Xie, Michael Givens, Fu Tang, Xiaoqiang Jiang, A. Subirats, Adrian Chasin, L.-Å. Ragnarsson, Naoto Horiguchi, B. Kaczer, D. Linten, Nadine Collaert	2017	10
18	Impact of channel thickness scaling on the performance of GaN-on-Si RF HEMTs on highly C-doped GaN buffer A. Alian, R. Rodríguez, Sachin Yadav, Uthayasankaran Peralagu, A. Sibaja Hernandez, V. Putcha, Ming Zhao, Rana ElKashlan, Bjorn Vermeersch, Hao Yu, E. Bury, Ahmad Khaled, Nadine Collaert, Bertrand Parvais	2022	9
19	BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors Adrian Chasin, J. Franco, B. Kaczer, V. Putcha, Pieter Weckx, R. Ritzenthaler, Hans Mertens, Naoto Horiguchi, Dimitri Linten, G. Rzepa	2017	9
20	Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications VUBIR (Vrije Universiteit Brussel) ·V. Putcha, E. Bury, J. Franco, A. Walke, Simeng E. Zhao, Uthayasankaran Peralagu, Ming Zhao, A. Alian, B. Kaczer, Niamh Waldron, D. Linten, Bertrand Parvais, Nadine Collaert	2020	9

About V. Putcha

V. Putcha is a scholar working on Electrical and Electronic Engineering, Condensed Matter Physics, Materials Chemistry, Atomic and Molecular Physics, and Optics and Electronic, Optical and Magnetic Materials, having authored 42 papers that have together received 542 indexed citations. Recurring topics across this work include Semiconductor materials and devices (38 papers), Advancements in Semiconductor Devices and Circuit Design (24 papers), GaN-based semiconductor devices and materials (14 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers), Ferroelectric and Negative Capacitance Devices (7 papers), Radio Frequency Integrated Circuit Design (4 papers), Electronic and Structural Properties of Oxides (4 papers) and Semiconductor Quantum Structures and Devices (3 papers). The work is most often cited by research in Condensed Matter Physics (151 citations), Electrical and Electronic Engineering (495 citations), Electronic, Optical and Magnetic Materials (51 citations), Hardware and Architecture (13 citations) and Materials Chemistry (87 citations). V. Putcha has collaborated with scholars based in Belgium, United States and Austria. Frequent co-authors include Nadine Collaert, Bertrand Parvais, D. Linten, J. Franco, B. Kaczer, Niamh Waldron, A. Alian, Pieter Weckx, Uthayasankaran Peralagu and G. Groeseneken. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Transactions on Nuclear Science, Journal of Applied Physics, Microelectronics Reliability and Semiconductor Science and Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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