A. Cros

1.3k citations

32 papers · 362 · h-index 12

Impact in

Electrical and Electronic Engineering top 10%
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
Hardware and Architecture

Papers in

Electrical and Electronic Engineering 32
- Advancements in Semiconductor Devices and Circuit Design 32
- Semiconductor materials and devices 32
- Integrated Circuits and Semiconductor Failure Analysis 13
- Silicon Carbide Semiconductor Technologies 5
- Ferroelectric and Negative Capacitance Devices 2
- Low-power high-performance VLSI design 2
- Electrostatic Discharge in Electronics 2
Atomic and Molecular Physics, and Optics 3
- Surface and Thin Film Phenomena 2

Co-authors: G. Ghibaudo (16 shared papers)José M. de la Rosa (4 shared papers)X. Federspiel (5 shared papers)E. Josse (7 shared papers)Augustin Cathignol (2 shared papers)Gyu‐Tae Kim (5 shared papers)Mireille Mouis (5 shared papers)Minju Shin (5 shared papers)
Journals: Solid-State Electronics (10 papers)IEEE Transactions on Electron Devices (2 papers)Journal of Computational Electronics (1 paper)IEEE Electron Device Letters (1 paper)IEEE Transactions on Nanotechnology (1 paper)
Partner nations: France Switzerland United States

In The Last Decade

A. Cros

30 papers receiving 353 citations

Peers

Countries citing papers authored by A. Cros

Since Specialization

Citations

This map shows the geographic impact of A. Cros's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by A. Cros with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites A. Cros more than expected).

Fields of papers citing papers by A. Cros

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by A. Cros. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by A. Cros. The network helps show where A. Cros may publish in the future.

Co-authors

The 25 scholars most cited alongside A. Cros, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with A. Cros Line = papers co-authored together A. Cros links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 32 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset D. Angot, V. Huard, Lama Rahhal, A. Cros, X. Federspiel, A. Bajolet, Y. Carminati, M. Saliva, E. Pion, F. Cacho, A. Bravaix	2013	57
2	A New Technique to Extract the Source/Drain Series Resistance of MOSFETs IEEE Electron Device Letters ·D. Fleury, A. Cros, G. Bidal, José M. de la Rosa, G. Ghibaudo	2009	51
3	Abnormally high local electrical fluctuations in heavily pocket-implanted bulk long MOSFET Solid-State Electronics ·Augustin Cathignol, S. Bordez, A. Cros, Krysten Rochereau, G. Ghibaudo	2009	25
4	First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration Dominique Golanski, P. Fonteneau, C. Fenouillet-Béranger, A. Cros, F. Monsieur, Nicolas Guitard, Charles-Alexandre Legrand, A. Dray, C. Richier, Helene Beckrich, P. Mora, G. Bidal, O. Weber, O. Saxod, Jean–Robert Manouvrier, Philippe Galy, N. Planes, F. Arnaud	2013	23
5	Low temperature characterization of mobility in 14 nm FD-SOI CMOS devices under interface coupling conditions Solid-State Electronics ·Minju Shin, Ming Shi, Mireille Mouis, A. Cros, E. Josse, Gyu‐Tae Kim, G. Ghibaudo	2015	22
6	New Y -function based MOSFET parameter extraction method from weak to strong inversion range Solid-State Electronics ·Jean-Baptiste Henry, Quentin Rafhay, A. Cros, G. Ghibaudo	2016	21
7	“Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction Solid-State Electronics ·C. Diouf, A. Cros, S. Monfray, Jérôme Mitard, José M. de la Rosa, D. Gloria, G. Ghibaudo	2013	19
8	In depth characterization of electron transport in 14 nm FD-SOI CMOS devices Solid-State Electronics ·Minju Shin, Ming Shi, Mireille Mouis, A. Cros, E. Josse, Gyu‐Tae Kim, G. Ghibaudo	2015	17
9	Automatic Extraction Methodology for Accurate Measurements of Effective Channel Length on 65-nm MOSFET Technology and Below IEEE Transactions on Semiconductor Manufacturing ·Dominique Fleury, A. Cros, Krunoslav Romanjek, David P. Roy, F. Perrier, Benjamin Dumont, H. Brut, G. Ghibaudo	2008	16
10	Electrical transport characterization of nano CMOS devices with ultra-thin silicon film HAL (Le Centre pour la Communication Scientifique Directe) ·G. Ghibaudo, M. Mouis, Loan Pham-Nguyen, K. Bennamane, Ilias O. Pappas, A. Cros, G. Bidal, Dominique Fleury, A. Claverie, G. Benassayag, Pier‐Francesco Fazzini, C. Fenouillet-Béranger, S. Monfray, (unknown), S. Cristoloveanu, T. Skotnicki, Nadine Collaert	2009	15
11	Comment on “Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology” IEEE Transactions on Electron Devices ·Terence B. Hook, Jeffrey B. Johnson, Augustin Cathignol, A. Cros, Gérard Ghibaudo	2011	13
12	Application of compact HCI model to prediction of process effect in 28FDSOI technology W. Arfaoui, X. Federspiel, A. Bravaix, P. Mora, A. Cros, D. Roy	2014	11
13	Modeling self-heating effects in advanced CMOS nodes M. Arabi, A. Cros, X. Federspiel, Cheikh Ndiaye, V. Huard, M. Rafik	2018	9
14	Experimental and Theoretical Investigation of Magnetoresistance From Linear Regime to Saturation in 14-nm FD-SOI MOS Devices IEEE Transactions on Electron Devices ·Minju Shin, Ming Shi, Mireille Mouis, A. Cros, E. Josse, Sutirtha Mukhopadhyay, B. A. Piot, Gyu‐Tae Kim, Gérard Ghibaudo	2014	9
15	Full split C–V method for parameter extraction in ultra thin BOX FDSOI MOS devices Solid-State Electronics ·Minju Shin, Ming Shi, Mireille Mouis, A. Cros, E. Josse, Gyu‐Tae Kim, G. Ghibaudo	2014	8
16	Mobility coupling effects due to remote Coulomb scattering in thin‐film FD‐SOI CMOS devices Electronics Letters ·K. Bennamane, I. Ben Akkez, A. Cros, C. Fenouillet-Béranger, F. Balestra, G. Ghibaudo	2013	6
17	Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility Journal of Computational Electronics ·Olivier Nier, D. Rideau, Yann‐Michel Niquet, F. Monsieur, Việt Hùng Nguyễn, François Triozon, A. Cros, R. Clerc, J. C. Barbé, Pierpaolo Palestri, David Esseni, Ivan Duchemin, Lee Smith, Luca Silvestri, Frédéric Nallet, C. Tavernier, H. Jaouen, L. Selmi	2013	6
18	A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs HAL (Le Centre pour la Communication Scientifique Directe) ·Dominique Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, Gérard Ghibaudo	2009	6
19	BTI induced dispersion: Challenges and opportunities for SRAM bit cell optimization F. Cacho, A. Cros, X. Federspiel, V. Huard, C. Roma	2016	5
20	Magnetoresistance mobility characterization in advanced FD-SOI n-MOSFETs Solid-State Electronics ·Minju Shin, Ming Shi, Mireille Mouis, A. Cros, E. Josse, Sutirha Mukhopadhyay, B. A. Piot, Gyu‐Tae Kim, G. Ghibaudo	2014	5

About A. Cros

A. Cros is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Biomedical Engineering, Infectious Diseases and Organic Chemistry, having authored 32 papers that have together received 362 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (32 papers), Semiconductor materials and devices (32 papers), Integrated Circuits and Semiconductor Failure Analysis (13 papers), Silicon Carbide Semiconductor Technologies (5 papers), Ferroelectric and Negative Capacitance Devices (2 papers), Low-power high-performance VLSI design (2 papers), Surface and Thin Film Phenomena (2 papers) and Electrostatic Discharge in Electronics (2 papers). The work is most often cited by research in Electrical and Electronic Engineering (356 citations), Hardware and Architecture (24 citations), Atomic and Molecular Physics, and Optics (29 citations), Biomedical Engineering (40 citations) and Condensed Matter Physics (7 citations). A. Cros has collaborated with scholars based in France, Switzerland and United States. Frequent co-authors include G. Ghibaudo, José M. de la Rosa, X. Federspiel, E. Josse, Augustin Cathignol, Gyu‐Tae Kim, Mireille Mouis, Minju Shin, V. Huard and A. Bravaix. Their work appears in journals such as Solid-State Electronics, IEEE Transactions on Electron Devices, Journal of Computational Electronics, IEEE Electron Device Letters and IEEE Transactions on Nanotechnology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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