D. Moy

699 citations

31 papers · 395 · h-index 11

Impact in

Hardware and Architecture top 10%
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Silicon and Solar Cell Technologies

Papers in

Electrical and Electronic Engineering 31
- Semiconductor materials and devices 19
- Advancements in Semiconductor Devices and Circuit Design 13
- Integrated Circuits and Semiconductor Failure Analysis 9
- Low-power high-performance VLSI design 4
- Advancements in Photolithography Techniques 4
- Advanced Memory and Neural Computing 4
Atomic and Molecular Physics, and Optics 8
- Semiconductor materials and interfaces 7

Co-authors: B. Davari (5 shared papers)Yuan Taur (4 shared papers)J.Y.-C. Sun (3 shared papers)M.R. Wordeman (4 shared papers)T. Kirihata (7 shared papers)M.R. Polcari (3 shared papers)Subramanian S. Iyer (6 shared papers)Ching-Fang Hsu (1 shared paper)
Journals: IEEE Electron Device Letters (2 papers)Applied Physics Letters (2 papers)IEEE Transactions on Electron Devices (2 papers)Japanese Journal of Applied Physics (1 paper)IEEE Transactions on Device and Materials Reliability (1 paper)
Partner nations: United States South Korea Sweden

In The Last Decade

D. Moy

29 papers receiving 376 citations

Peers

Countries citing papers authored by D. Moy

Since Specialization

Citations

This map shows the geographic impact of D. Moy's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Moy with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Moy more than expected).

Fields of papers citing papers by D. Moy

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by D. Moy. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Moy. The network helps show where D. Moy may publish in the future.

Co-authors

The 25 scholars most cited alongside D. Moy, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with D. Moy Line = papers co-authored together D. Moy links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Showing the 20 most-cited of 31 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A high-performance 0.25- mu m CMOS technology. II. Technology IEEE Transactions on Electron Devices ·B. Davari, Wei‐Hsu Chang, Karen Petrillo, C. Y. Wong, D. Moy, Yuan Taur, M.R. Wordeman, J.Y.-C. Sun, Ching-Fang Hsu, M.R. Polcari	1992	85
2	Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips Norm Robson, John Safran, C. Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, A. Leslie, D. Moy, T. Kirihata, Subramanian S. Iyer	2007	53
3	Source—Drain contact resistance in CMOS with self-aligned TiSi₂ IEEE Transactions on Electron Devices ·Yuan Taur, J.Y.-C. Sun, D. Moy, L.K. Wang, B. Davari, S. P. Klepner, C. Y. Ting	1987	45
4	High performance 0.1 μm CMOS devices with 1.5 V power supply Y. Taur, Shalom J. Wind, Y. J. Mii, Y. T. Lii, D. Moy, K.A. Jenkins, C.L. Chen, P. Coane, D. Klaus, J. J. Bucchignano, M.G. Rosenfield, M. G. R. Thomson, M.R. Polcari	2002	24
5	Experimental technology and characterization of self-aligned 0.1&#181;m-gate-length low-temperature operation NMOS devices G.A. Sai-Halasz, M.R. Wordeman, D. P. Kern, E. Ganin, S. A. Rishton, Hong Ng, D.S. Zicherman, D. Moy, T. H. P. Chang, R.H. Dennard	1987	21
6	A Compact eFUSE Programmable Array Memory for SOI CMOS John Safran, A. Leslie, Gregory Fredeman, C. Kothandaraman, Alberto Cestero, Xiang Chen, Raj Rajeevakumar, Deok‐kee Kim, Yan Zun Li, D. Moy, Norman Robson, T. Kirihata, Subramanian S. Iyer	2007	20
7	A 2 W, 65% PAE single-supply enhancement-mode power PHEMT for 3 V PCS applications Der-Woei Wu, R. Parkhurst, Shyh-Liang Fu, Jin Wei, Chung‐Yi Su, Shih-Shun Chang, D. Moy, William Brent Fields, P. W. Chye, R. Levitsky	2002	16
8	Novel self-aligned W/TiN/TiSi2 contact structure for very shallow junctions and interconnections Applied Physics Letters ·(unknown), D. Moy, S. Brodsky, A. Charaı̈, L. Krusin‐Elbaum, P.J. Restle, Thien Nguyen, C. S. Oh	1989	13
9	Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies IEEE Electron Device Letters ·Faraz Khan, Min Han, D. Moy, Robert Katz, Jiang Liu, Edmund Banghart, Norman Robson, T. Kirihata, Jason C. S. Woo, Subramanian S. Iyer	2019	12
10	Inverter performance of deep-submicrometer MOSFETs IEEE Electron Device Letters ·G.A. Sai-Halasz, M.R. Wordeman, D. P. Kern, S. A. Rishton, E. Ganin, Hong Ng, D. Moy, T. H. P. Chang, R.H. Dennard	1988	11
11	Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications C. Kothandaraman, X. Chen, D. Moy, D. Lea, Sami Rosenblatt, Faraz Khan, Derek Leu, T. Kirihata, Dimitris P. Ioannou, G. LaRosa, Jeffrey B. Johnson, Norman Robson, Subramanian S. Iyer	2015	11
12	80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, Faraz Khan, T. Kirihata, Subramanian Iyer	2016	10
13	High performance 0.18 μm SOI CMOS technology E. Leobandung, E. Barth, M. Sherony, Shih-Hsuan Lo, R. Schulz, Wen-Ting Chu, Mukesh Khare, D. K. Sadana, D. Schepis, R. Boiam, I. Sleight, F. White, F. Assaderaghi, D. Moy, G. Biery, R. Goldblan, T.-C. Chen, B. Davari, G. Shahidi	2003	9
14	0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography L. K. Wang, Y. Taur, D. Moy, R.H. Dennard, Kaolin N. Chiong, F. J. Hohn, P. Coane, A. Edenfeld, S. Carbaugh, Donald P. Kenney, Sebastian Schnur	1986	9
15	Study of contact and shallow junction characteristics in submicron CMOS with self-aligned titanium silicide IBM Journal of Research and Development ·Yuan Taur, B. Davari, D. Moy, J.Y.-C. Sun, C. Y. Ting	1987	7
16	80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity IEEE Journal of Solid-State Circuits ·Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, Faraz Khan, T. Kirihata, Subramanian S. Iyer	2018	7
17	Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond Faraz Khan, D. Moy, D. Anand, E.H. Schroeder, Robert Katz, Jiang Liu, Edmund Banghart, Norman Robson, T. Kirihata	2019	6
18	Reliability Investigation of NiPtSi Electrical Fuse With Different Programming Mechanisms IEEE Transactions on Device and Materials Reliability ·Chunyan Tian, D. Moy, Chuck Le, Brian Messenger, C. Kothandaraman, John Safran, S. Wu, Norman Robson, Subramanian S. Iyer	2008	6
19	A high performance 0.25 mu m CMOS technology B. Davari, Wei‐Hsu Chang, M.R. Wordeman, Chong-In Oh, Yuan Taur, Karen Petrillo, D. Moy, J. J. Bucchignano, Hong Ng, M.G. Rosenfield, F. J. Hohn, Manuel de León Rodríguez	2003	5
20	The Application of Deep UV Phase Shifted-Single Layer Halftone Reticles to 256 Mbit Dynamic Random Access Memory Cell Patterns Japanese Journal of Applied Physics ·Kohji Hashimoto, Donald J. Samuels, Timothy R. Farrell, D. Moy, Ronald M. Martino, Richard A. Ferguson, Takashi Sato Maurer	1994	5

About D. Moy

D. Moy is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics, Biomedical Engineering, Hardware and Architecture and Electronic, Optical and Magnetic Materials, having authored 31 papers that have together received 395 indexed citations. Recurring topics across this work include Semiconductor materials and devices (19 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers), Integrated Circuits and Semiconductor Failure Analysis (9 papers), Semiconductor materials and interfaces (7 papers), Low-power high-performance VLSI design (4 papers), Advancements in Photolithography Techniques (4 papers), Advanced Memory and Neural Computing (4 papers) and Copper Interconnects and Reliability (3 papers). The work is most often cited by research in Hardware and Architecture (47 citations), Electrical and Electronic Engineering (372 citations), Atomic and Molecular Physics, and Optics (88 citations), Electronic, Optical and Magnetic Materials (22 citations) and Condensed Matter Physics (13 citations). D. Moy has collaborated with scholars based in United States, South Korea and Sweden. Frequent co-authors include B. Davari, Yuan Taur, J.Y.-C. Sun, M.R. Wordeman, T. Kirihata, M.R. Polcari, Subramanian S. Iyer, Ching-Fang Hsu, C. Y. Wong and Wei‐Hsu Chang. Their work appears in journals such as IEEE Electron Device Letters, Applied Physics Letters, IEEE Transactions on Electron Devices, Japanese Journal of Applied Physics and IEEE Transactions on Device and Materials Reliability.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

D. Moy

Impact in

Papers in i

In The Last Decade

D. Moy

Peers

Countries citing papers authored by D. Moy

Fields of papers citing papers by D. Moy

All Works

About D. Moy

Explore authors with similar magnitude of impact

Papers in