P. Hazucha

3.5k citations

34 papers · 2.8k · 2 hit papers · h-index 22

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 1%
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Advanced DC-DC Converters
- Radio Frequency Integrated Circuit Design

Papers in

Electrical and Electronic Engineering 34
- Low-power high-performance VLSI design 14
- Radiation Effects in Electronics 13
- Semiconductor materials and devices 11
- Advanced DC-DC Converters 8
- Radio Frequency Integrated Circuit Design 7
- Advancements in Semiconductor Devices and Circuit Design 6
Biomedical Engineering 15
- Analog and Mixed-Signal Circuit Design 15

Co-authors: Tanay Karnik (26 shared papers)C. Svensson (6 shared papers)Shekhar Borkar (12 shared papers)B. Bloechel (9 shared papers)G. Schrom (15 shared papers)Donald S. Gardner (13 shared papers)D. Finan (2 shared papers)G. Dermer (7 shared papers)
Journals: IEEE Journal of Solid-State Circuits (9 papers)IEEE Transactions on Nuclear Science (3 papers)IEEE Transactions on Magnetics (1 paper)IEEE Transactions on Dependable and Secure Computing (1 paper)Journal of Applied Physics (1 paper)
Partner nations: United States Sweden Canada

In The Last Decade

P. Hazucha

34 papers receiving 2.7k citations

P. Hazucha's Hit Papers

align trajectories log scale

Characterization of soft errors caused by single event upsets in CMOS processes 2004 · 412 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2004 IEEE Transactions on Dependable and Secure Computing
2000 IEEE Transactions on Nuclear Science

Peers

Countries citing papers authored by P. Hazucha

Since Specialization

Citations

This map shows the geographic impact of P. Hazucha's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Hazucha with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Hazucha more than expected).

Fields of papers citing papers by P. Hazucha

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Hazucha. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Hazucha. The network helps show where P. Hazucha may publish in the future.

Co-authors

The 25 scholars most cited alongside P. Hazucha, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with P. Hazucha Line = papers co-authored together P. Hazucha links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 34 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Impact of CMOS technology scaling on the atmospheric neutron soft error rate IEEE Transactions on Nuclear Science ·P. Hazucha, C. Svensson Hit paper breakdown →	2000	488
2	Area-efficient linear regulator with ultra-fast load regulation IEEE Journal of Solid-State Circuits ·P. Hazucha, Tanay Karnik, B. Bloechel, C. Parsons, D. Finan, Shekhar Borkar	2005	460
3	Characterization of soft errors caused by single event upsets in CMOS processes IEEE Transactions on Dependable and Secure Computing ·Tanay Karnik, P. Hazucha Hit paper breakdown →	2004	412
4	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package IEEE Journal of Solid-State Circuits ·P. Hazucha, G. Schrom, Jaehong Hahn, B. Bloechel, P. Hack, G. Dermer, S. Narendra, Donald S. Gardner, Tanay Karnik, Vivek De, Shekhar Borkar	2005	251
5	Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation P. Hazucha, Tanay Karnik, J. Maiz, S.V. Walstra, B. Bloechel, James Tschanz, G. Dermer, S.A. Hareland, Peter R. Armstrong, Shekhar Borkar	2004	125
6	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process IEEE Journal of Solid-State Circuits ·P. Hazucha, Tanay Karnik, S.V. Walstra, B. Bloechel, James Tschanz, J. Maiz, K. Soumyanath, G. Dermer, S. Narendra, Vivek De, Shekhar Borkar	2004	97
7	Integrated on-chip inductors using magnetic material (invited) Journal of Applied Physics ·Donald S. Gardner, G. Schrom, P. Hazucha, Fabrice Paillet, Tanay Karnik, Shekhar Borkar, Roy Hallstein, Tony Dambrauskas, Charles Hill, Clark Linde, Wojciech Worwag, Robert Baresel, Sriram Muthukumar	2008	94
8	A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551) ·G. Schrom, P. Hazucha, Jaehong Hahn, Donald S. Gardner, B. Bloechel, G. Dermer, S. Narendra, Tanay Karnik, Vivek De	2004	84
9	A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters IEEE Journal of Solid-State Circuits ·Pengfei Li, Xue Lin, P. Hazucha, Tanay Karnik, Rizwan Bashirullah	2009	74
10	Integrated On-Chip Inductors With Magnetic Films IEEE Transactions on Magnetics ·Donald S. Gardner, G. Schrom, P. Hazucha, Fabrice Paillet, Tanay Karnik, Shekhar Borkar	2007	71
11	Cosmic-ray soft error rate characterization of a standard 0.6-/spl mu/m CMOS process IEEE Journal of Solid-State Circuits ·P. Hazucha, C. Svensson, S.A. Wender	2000	67
12	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process P. Hazucha, Tanay Karnik, S.V. Walstra, B. Bloechel, James Tschanz, J. Maiz, K. Soumyanath, G. Dermer, S. Narendra, Vivek De, Shekhar Borkar	2004	58
13	High-Voltage Power Delivery Through Charge Recycling IEEE Journal of Solid-State Circuits ·S. Rajapandian, Kenneth L. Shepard, P. Hazucha, Tanay Karnik	2006	58
14	A 100MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors Conference proceedings/Conference proceedings - IEEE Applied Power Electronics Conference and Exposition ·G. Schrom, P. Hazucha, Fabrice Paillet, David J. Rennie, S.T. Moon, Donald S. Gardner, T. Kamik, Pengju Sun, Trung-Thu Nguyen, Michael J. Hill, Kaladhar Radhakrishnan, Tolga Memioğlu	2007	52
15	Selective node engineering for chip-level soft error rate improvement [in CMOS] Tanay Karnik, Sriram Vangal, V. Veeramachaneni, P. Hazucha, Vasantha Erraguntla, Shekhar Borkar	2003	50
16	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·G. Schrom, P. Hazucha, Jaehong Hahn, Volkan Kursun, Donald S. Gardner, S. Narendra, Tanay Karnik, Vivek De	2004	50
17	High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters IEEE Journal of Solid-State Circuits ·P. Hazucha, Sung Tae Moon, G. Schrom, Fabrice Paillet, Donald S. Gardner, S. Rajapandian, Tanay Karnik	2007	49
18	Optimal Design of Monolithic Integrated DC-DC Converters G. Schrom, P. Hazucha, Fabrice Paillet, Donald S. Gardner, S.T. Moon, Tanay Karnik	2006	44
19	High-tension power delivery: operating 0.18μm CMOS digital logic at 5.4V S. Rajapandian, Kenneth L. Shepard, P. Hazucha, Tanay Karnik	2005	38
20	Integrated On-Chip Inductors with Magnetic Films SMARTech Repository (Georgia Institute of Technology) ·Donald S. Gardner, G. Schrom, P. Hazucha, Fabrice Paillet, Tanay Karnik, Shekhar Borkar, Jason Saulters, Jordan Owens, Jeff Wetzel	2006	35

About P. Hazucha

P. Hazucha is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Hardware and Architecture, Automotive Engineering and Pulmonary and Respiratory Medicine, having authored 34 papers that have together received 2.8k indexed citations. Recurring topics across this work include Analog and Mixed-Signal Circuit Design (15 papers), Low-power high-performance VLSI design (14 papers), Radiation Effects in Electronics (13 papers), Semiconductor materials and devices (11 papers), Advanced DC-DC Converters (8 papers), VLSI and Analog Circuit Testing (7 papers), Radio Frequency Integrated Circuit Design (7 papers) and Advancements in Semiconductor Devices and Circuit Design (6 papers). The work is most often cited by research in Hardware and Architecture (891 citations), Electrical and Electronic Engineering (2.7k citations), Biomedical Engineering (727 citations), Software (57 citations) and Safety, Risk, Reliability and Quality (95 citations). P. Hazucha has collaborated with scholars based in United States, Sweden and Canada. Frequent co-authors include Tanay Karnik, C. Svensson, Shekhar Borkar, B. Bloechel, G. Schrom, Donald S. Gardner, D. Finan, G. Dermer, Vivek De and S. Narendra. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Nuclear Science, IEEE Transactions on Magnetics, IEEE Transactions on Dependable and Secure Computing and Journal of Applied Physics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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P. Hazucha's Hit Papers

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