D. Plass
Impact in
- Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
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- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
Papers in
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- Parallel Computing and Optimization Techniques 15
- VLSI and Analog Circuit Testing 2
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- Low-power high-performance VLSI design 27
- Advancements in Semiconductor Devices and Circuit Design 5
- VLSI and FPGA Design Techniques 3
- Integrated Circuits and Semiconductor Failure Analysis 1
- Co-authors
- Y.H. Chan (9 shared papers)Ching-Te Kent Chuang (3 shared papers)Eric J. Fluhr (4 shared papers)Joshua Friedrich (3 shared papers)Rajiv Joshi (2 shared papers)William Huott (4 shared papers)Jack Dilullo (2 shared papers)A. Devgan (1 shared paper)
- Journals
- IEEE Journal of Solid-State Circuits (4 papers)IBM Journal of Research and Development (3 papers)Proceedings - IEEE International SOI Conference/Proceedings (1 paper)European Solid-State Device Research Conference (1 paper)IEEE Symposium on VLSI Circuits (VLSI-Circuits) (2 papers)
- Partner nations
- United StatesGermanyIndia
In The Last Decade
D. Plass
28 papers receiving 614 citations
Peers
Comparison fields: 5 of 21
- Hardware and Architecture 229
- Electrical and Electronic Engineering 477
- Computer Networks and Communications 59
- Biomedical Engineering 31
- Statistics, Probability and Uncertainty 5
Countries citing papers authored by D. Plass
This map shows the geographic impact of D. Plass's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by D. Plass with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites D. Plass more than expected).
Fields of papers citing papers by D. Plass
This network shows the impact of papers produced by D. Plass. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by D. Plass. The network helps show where D. Plass may publish in the future.
Co-authors
The 25 scholars most cited alongside D. Plass, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
Showing the 20 most-cited of 29 papers — load more, or switch the sort, to bring in the rest.
| # | Work | ||
|---|---|---|---|
| 1 | 2004 | 94 | |
| 2 | 2007 | 93 | |
| 3 | 2007 | 48 | |
| 4 | 2014 | 41 | |
| 5 | 2014 | 40 | |
| 6 | 2004 | 37 | |
| 7 | 2013 | 28 | |
| 8 | 2009 | 25 | |
| 9 | 2015 | 23 | |
| 10 | 2011 | 22 | |
| 11 | 2004 | 21 | |
| 12 | 2006 | 18 | |
| 13 | 2007 | 18 | |
| 14 | 2006 | 17 | |
| 15 | 2013 | 16 | |
| 16 | 2017 | 16 | |
| 17 | 2015 | 15 | |
| 18 | 2017 | 15 | |
| 19 | Design and Implementation of the POWER5 TM Microprocessor | 2004 | 12 |
| 20 | 2006 | 11 |
About D. Plass
D. Plass is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Biomedical Engineering and Nuclear Energy and Engineering, having authored 29 papers that have together received 647 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (27 papers), Parallel Computing and Optimization Techniques (15 papers), Advancements in Semiconductor Devices and Circuit Design (5 papers), VLSI and FPGA Design Techniques (3 papers), VLSI and Analog Circuit Testing (2 papers), Interconnection Networks and Systems (2 papers), Integrated Circuits and Semiconductor Failure Analysis (1 paper) and Analog and Mixed-Signal Circuit Design (1 paper). The work is most often cited by research in Hardware and Architecture (229 citations), Electrical and Electronic Engineering (477 citations), Computer Networks and Communications (59 citations), Biomedical Engineering (31 citations) and Statistics, Probability and Uncertainty (5 citations). D. Plass has collaborated with scholars based in United States, Germany and India. Frequent co-authors include Y.H. Chan, Ching-Te Kent Chuang, Eric J. Fluhr, Joshua Friedrich, Rajiv Joshi, William Huott, Jack Dilullo, A. Devgan, Pramod Kumar Patel and Subhas Chandra Mukhopadhyay. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IBM Journal of Research and Development, Proceedings - IEEE International SOI Conference/Proceedings, European Solid-State Device Research Conference and IEEE Symposium on VLSI Circuits (VLSI-Circuits).
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.