Steve Runyon
Impact in
- Hardware and Architecture top 5%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
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- Numerical Methods and Algorithms
Papers in
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- VLSI and Analog Circuit Testing 2
- Parallel Computing and Optimization Techniques 2
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- Low-power high-performance VLSI design 3
- Integrated Circuits and Semiconductor Failure Analysis 1
- VLSI and FPGA Design Techniques 1
- 3D IC and TSV technologies 1
- Co-authors
- Robert K. Montoye (2 shared papers)E. Hökenek (2 shared papers)J. DiLullo (2 shared papers)P.J. Restle (2 shared papers)H.H. Smith (1 shared paper)M. Sweet (1 shared paper)Balaram Sinharoy (1 shared paper)P. J. Camporese (1 shared paper)
- Journals
- IBM Journal of Research and Development (2 papers)IEEE Spectrum (1 paper)IEEE Computer Society Press eBooks (1 paper)
- Partner nations
- United StatesGermany
In The Last Decade
Steve Runyon
5 papers receiving 217 citations
Peers
Comparison fields: 5 of 25
- Hardware and Architecture 132
- Computational Theory and Mathematics 152
- Signal Processing 63
- Electrical and Electronic Engineering 160
- Computational Mathematics 1
Countries citing papers authored by Steve Runyon
This map shows the geographic impact of Steve Runyon's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Steve Runyon with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Steve Runyon more than expected).
Fields of papers citing papers by Steve Runyon
This network shows the impact of papers produced by Steve Runyon. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Steve Runyon. The network helps show where Steve Runyon may publish in the future.
Co-authors
The 20 scholars most cited alongside Steve Runyon, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 1990 | 153 | |
| 2 | Design of the IBM RISC System/6000 floating-point execution unit | 1995 | 34 |
| 3 | 2007 | 20 | |
| 4 | 1999 | 16 | |
| 5 | Design and Implementation of the POWER5 TM Microprocessor | 2004 | 12 |
About Steve Runyon
Steve Runyon is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Computational Theory and Mathematics and Control and Systems Engineering, having authored 5 papers that have together received 235 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (3 papers), VLSI and Analog Circuit Testing (2 papers), Parallel Computing and Optimization Techniques (2 papers), Numerical Methods and Algorithms (2 papers), Integrated Circuits and Semiconductor Failure Analysis (1 paper), Engineering and Test Systems (1 paper), VLSI and FPGA Design Techniques (1 paper) and 3D IC and TSV technologies (1 paper). The work is most often cited by research in Hardware and Architecture (132 citations), Computational Theory and Mathematics (152 citations), Signal Processing (63 citations), Electrical and Electronic Engineering (160 citations) and Computational Mathematics (1 citation). Steve Runyon has collaborated with scholars based in United States and Germany. Frequent co-authors include Robert K. Montoye, E. Hökenek, J. DiLullo, P.J. Restle, H.H. Smith, M. Sweet, Balaram Sinharoy, P. J. Camporese, R. M. Averill and J. Clabes. Their work appears in journals such as IBM Journal of Research and Development, IEEE Spectrum and IEEE Computer Society Press eBooks.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.