G. E. Dermer

1.1k citations

21 papers · 914 · h-index 13

Impact in

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 5%
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- Advanced DC-DC Converters
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design

Papers in

Hardware and Architecture 10
- Parallel Computing and Optimization Techniques 5
- VLSI and Analog Circuit Testing 5
Electrical and Electronic Engineering 16
- Low-power high-performance VLSI design 9
- Semiconductor materials and devices 7
- Radiation Effects in Electronics 4
- Advancements in Semiconductor Devices and Circuit Design 4

Co-authors: B. Bloechel (14 shared papers)Tanay Karnik (7 shared papers)P. Hazucha (7 shared papers)Shekhar Y. Borkar (11 shared papers)S. Narendra (11 shared papers)Vivek K. De (11 shared papers)James W. Tschanz (7 shared papers)G. Schrom (3 shared papers)
Journals: IEEE Journal of Solid-State Circuits (4 papers)ACM SIGPLAN Notices (1 paper)ACM SIGOPS Operating Systems Review (1 paper)ACM SIGARCH Computer Architecture News (1 paper)2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551) (1 paper)
Partner nations: United States

In The Last Decade

G. E. Dermer

21 papers receiving 871 citations

Peers

Countries citing papers authored by G. E. Dermer

Since Specialization

Citations

This map shows the geographic impact of G. E. Dermer's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by G. E. Dermer with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites G. E. Dermer more than expected).

Fields of papers citing papers by G. E. Dermer

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by G. E. Dermer. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by G. E. Dermer. The network helps show where G. E. Dermer may publish in the future.

Co-authors

The 25 scholars most cited alongside G. E. Dermer, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with G. E. Dermer Line = papers co-authored together G. E. Dermer links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 21 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package IEEE Journal of Solid-State Circuits ·P. Hazucha, G. Schrom, Jaehong Hahn, B. Bloechel, P. Hack, G. E. Dermer, S. Narendra, Donald S. Gardner	2005	252
2	Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation P. Hazucha, Tanay Karnik, Jose A. Maiz, S.V. Walstra, B. Bloechel, James W. Tschanz, G. E. Dermer, Scott A. Hareland	2004	122
3	Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process IEEE Journal of Solid-State Circuits ·P. Hazucha, Tanay Karnik, S.V. Walstra, B. Bloechel, James W. Tschanz, Jose A. Maiz, Krishnamurthy Soumyanath, G. E. Dermer	2004	95
4	A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551) ·G. Schrom, P. Hazucha, Jaehong Hahn, Donald S. Gardner, B. Bloechel, G. E. Dermer, S. Narendra, Tanay Karnik	2004	85
5	Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swapped-body biasing technique S. Narendra, James W. Tschanz, J. Hofsheier, B. Bloechel, Sriram R. Vangal, Yatin Hoskote, Sai Chun Tang, Dinesh Somasekhar	2004	68
6	The ZS-1 central processor ACM SIGARCH Computer Architecture News ·James E. Smith, G. E. Dermer, B. D. Vanderwarn, Stefan Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James P. Laudon	1987	66
7	Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process P. Hazucha, Tanay Karnik, S.V. Walstra, B. Bloechel, James W. Tschanz, Jose A. Maiz, Krishnamurthy Soumyanath, G. E. Dermer	2004	56
8	1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·S. Narendra, M. Haycock, Venkatesh Govindarajulu, Vasantha Erraguntla, H. Wilson, Sriram R. Vangal, A. Pangal, Erik Seligman	2003	41
9	A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS IEEE Journal of Solid-State Circuits ·Yatin Hoskote, B. Bloechel, G. E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, D. Klowden, S. Narendra	2003	30
10	5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS IEEE Journal of Solid-State Circuits ·Sriram R. Vangal, Mark A Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, H. Wilson, A. Pangal	2002	26
11	The ZS-1 central processor James E. Smith, G. E. Dermer, B. D. Vanderwarn, Stefan Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James P. Laudon	1987	22
12	A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes Rahul Vivek Nair, Nitin Borkar, Colin Browning, G. E. Dermer, V. Eriaguntla, Venkatesh Govindarajulu, A. Pangal, J.D. Prijic	2002	14
13	Impact of body bias on alpha- and neutron-induced soft error rates of flip-flops Tanay Karnik, James W. Tschanz, B. Bloechel, P. Hazucha, Peter R. Armstrong, S. Narendra, Ali Reza Keshavarzi, Krishnamurthy Soumyanath	2004	13
14	A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications Dinesh Somasekhar, Shih‐Lien Lu, B. Bloechel, G. E. Dermer, K. Lai, Shekhar Y. Borkar, Vivek K. De	2005	6
15	A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·Sriram R. Vangal, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, H. Wilson, A. Pangal, V. Veeramachaneni	2003	6
16	The Astronautics ZS-1 processor James E. Smith, G. E. Dermer, B. D. Vanderwarn, Stefan Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James P. Laudon	2003	3
17	Bitline Leakage Compensation (BLC) and Leakage Reduction (BLR) Techniques for 23GHz On-Chip Cache Arrays in Microprocessors on 90nm Logic Technology Muhammad M. Khellah, Yibin Ye, Dinesh Somasekhar, D. Casper, B. Bloechel, Trang Thi Thu Nguyen, G. E. Dermer, Kangxin Zhang	2005	3
18	A 233MHz, 80-87% efficient, integrated, 4-phase DC-DC converter in 90nm CMOS P. Hazucha, G. Schrom, Jaehong Hahn, B. Bloechel, P. Hack, G. E. Dermer, S. Narendra, Donald S. Gardner	2004	3
19	The ZS-1 central processor ACM SIGOPS Operating Systems Review ·James E. Smith, G. E. Dermer, B. D. Vanderwarn, Stefan Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James P. Laudon	1987	1
20	The ZS-1 central processor ACM SIGPLAN Notices ·James E. Smith, G. E. Dermer, B. D. Vanderwarn, Stefan Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James P. Laudon	1987	1

About G. E. Dermer

G. E. Dermer is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Aerospace Engineering and Biomedical Engineering, having authored 21 papers that have together received 914 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (9 papers), Semiconductor materials and devices (7 papers), Parallel Computing and Optimization Techniques (5 papers), VLSI and Analog Circuit Testing (5 papers), Satellite Communication Systems (5 papers), Radiation Effects in Electronics (4 papers), Advancements in Semiconductor Devices and Circuit Design (4 papers) and Spacecraft Design and Technology (4 papers). The work is most often cited by research in Hardware and Architecture (330 citations), Electrical and Electronic Engineering (787 citations), Computer Networks and Communications (160 citations), Biomedical Engineering (169 citations) and Safety, Risk, Reliability and Quality (18 citations). G. E. Dermer has collaborated with scholars based in United States. Frequent co-authors include B. Bloechel, Tanay Karnik, P. Hazucha, Shekhar Y. Borkar, S. Narendra, Vivek K. De, James W. Tschanz, G. Schrom, Jaehong Hahn and Donald S. Gardner. Their work appears in journals such as IEEE Journal of Solid-State Circuits, ACM SIGPLAN Notices, ACM SIGOPS Operating Systems Review, ACM SIGARCH Computer Architecture News and 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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