Yen-Huei Chen

1.2k citations

27 papers · 865 · 1 hit paper · h-index 13

Impact in

Hardware and Architecture top 5%
- Parallel Computing and Optimization Techniques
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering top 5%
- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices

Papers in

Electrical and Electronic Engineering 25
- Semiconductor materials and devices 20
- Advancements in Semiconductor Devices and Circuit Design 17
- Low-power high-performance VLSI design 12
- Ferroelectric and Negative Capacitance Devices 9
- 3D IC and TSV technologies 3
- Advanced Memory and Neural Computing 3
Hardware and Architecture 6
- Parallel Computing and Optimization Techniques 4

Co-authors: Hung-Jen Liao (22 shared papers)Hidehiro Fujiwara (15 shared papers)Meng‐Fan Chang (6 shared papers)Tsung-Yung Jonathan Chang (7 shared papers)Jonathan Chang (12 shared papers)Dar Sun (6 shared papers)Yu-Der Chih (4 shared papers)Kerem Akarvardar (3 shared papers)
Journals: IEEE Journal of Solid-State Circuits (5 papers)2022 IEEE International Solid- State Circuits Conference (ISSCC) (1 paper)IEICE technical report. Speech (1 paper)IEEE Conference Proceedings (1 paper)
Partner nations: Taiwan United States Japan

In The Last Decade

Yen-Huei Chen

25 papers receiving 839 citations

Yen-Huei Chen's Hit Papers

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16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications 2021 · 206 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2021 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Peers

Countries citing papers authored by Yen-Huei Chen

Since Specialization

Citations

This map shows the geographic impact of Yen-Huei Chen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yen-Huei Chen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yen-Huei Chen more than expected).

Fields of papers citing papers by Yen-Huei Chen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yen-Huei Chen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yen-Huei Chen. The network helps show where Yen-Huei Chen may publish in the future.

Co-authors

The 25 scholars most cited alongside Yen-Huei Chen, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Yen-Huei Chen Line = papers co-authored together Yen-Huei Chen links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 27 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yulin Chen, Chieh-Pu Lo, Cheng-Han Lu, H. Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan‐Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yuxiao Wang, Meng‐Fan Chang, Tsung-Yung Jonathan Chang Hit paper breakdown →	2021	206
2	A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations 2022 IEEE International Solid- State Circuits Conference (ISSCC) ·Hidehiro Fujiwara, H. Mori, Wei-Chang Zhao, Mei‐Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan‐Li Chou, Mahmut E. Sinangil, Yuxiao Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2022	134
3	A 16 nm 128 Mb SRAM in High-$\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications IEEE Journal of Solid-State Circuits ·Yen-Huei Chen, Wei-Min Chan, (unknown), Hung-Jen Liao, (unknown), J.J. Liaw, (unknown), Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang	2014	113
4	A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme IEEE Journal of Solid-State Circuits ·Jui-Jen Wu, Yen-Huei Chen, Meng‐Fan Chang, Po-Wei Chou, Chien‐Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan‐Hua Chu, Wen-Chin Wu, H. Yamauchi	2011	65
5	A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update H. Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao‐Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan‐Li Chou, Hidehiro Fujiwara, Yuxiao Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	2023	52
6	A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V<inf>MIN</inf> applications Jun-Hao Chang, Yen-Huei Chen, Hsu-Yung Cheng, Wei-Min Chan, Hung-Jen Liao, Q. Li, S.Z. Chang, S. Natarajan, Rong‐Zau Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan‐Lun Cheng, Min Cao, George Chang	2013	51
7	12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V<inf>MIN</inf> applications Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu	2017	43
8	15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V_MIN Applications Jonathan Chang, Yen-Huei Chen, Gary Chan, Hank Cheng, Po‐Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li	2020	33
9	A large σV<inf>TH</inf>/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme Jui-Jen Wu, Yen-Huei Chen, Meng‐Fan Chang, Po-Wei Chou, Chien‐Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan‐Hua Chu, Wen-Chin Wu, H. Yamauchi	2010	25
10	A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V _MIN Applications IEEE Journal of Solid-State Circuits ·Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po‐Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li	2020	22
11	Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM IEEE Journal of Solid-State Circuits ·Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng‐Fan Chang, H. Yamauchi	2012	14
12	24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue Hidehiro Fujiwara, Chih‐Yu Lin, Hsien-Yu Pan, C.Y. Lin, Po-Yi Huang, Kao-Cheng Lin, J.J. Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang	2019	14
13	A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications Hidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Run Wu, Hung-Jen Liao, Jonathan Chang	2016	13
14	A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms IEEE Journal of Solid-State Circuits ·Meng‐Fan Chang, Chih-Sheng Lin, Wei-Cheng Wu, Ming-Pin Chen, Yen-Huei Chen, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Cha-Hsin Lin, H. Yamauchi	2013	12
15	A larger stacked layer number scalable TSV-based 3D-SRAM for high-performance universal-memory-capacity 3D-IC platforms Meng‐Fan Chang, Wei-Cheng Wu, Chih-Sheng Lin, Pi-Feng Chiu, Ming-Bin Chen, Yen-Huei Chen, Hsin-Chi Lai, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, H. Yamauchi	2011	10
16	A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, J.J. Liaw, Hung-Jen Liao, Jonathan Chang	2016	10
17	13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-V<inf>MIN</inf> applications Yen-Huei Chen, Wei-Min Chan, Wei‐Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, S. Natarajan, Jonathan Chang	2014	10
18	17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies Hidehiro Fujiwara, Liwen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, J.J. Liaw, Chih‐Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang	2015	9
19	Embedded memories for mobile, IoT, automotive and high performance computing Jonathan Chang, Hung-Jen Liao, Yu-Der Chih, Mahmut E. Sinangil, Yen-Huei Chen, M.A. Clinton, Shih‐Lien Lu	2017	8
20	A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-V_MIN Applications Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po‐Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, A. Katoch, Robin Lee, Hung-Jen Liao, J.J. Liaw, Shien-Yang Wu, Quincy Li	2023	7

About Yen-Huei Chen

Yen-Huei Chen is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Computational Theory and Mathematics and Infectious Diseases, having authored 27 papers that have together received 865 indexed citations. Recurring topics across this work include Semiconductor materials and devices (20 papers), Advancements in Semiconductor Devices and Circuit Design (17 papers), Low-power high-performance VLSI design (12 papers), Ferroelectric and Negative Capacitance Devices (9 papers), Parallel Computing and Optimization Techniques (4 papers), Advanced Data Storage Technologies (4 papers), 3D IC and TSV technologies (3 papers) and Advanced Memory and Neural Computing (3 papers). The work is most often cited by research in Hardware and Architecture (224 citations), Electrical and Electronic Engineering (785 citations), Computer Networks and Communications (83 citations), Computer Vision and Pattern Recognition (56 citations) and Artificial Intelligence (74 citations). Yen-Huei Chen has collaborated with scholars based in Taiwan, United States and Japan. Frequent co-authors include Hung-Jen Liao, Hidehiro Fujiwara, Meng‐Fan Chang, Tsung-Yung Jonathan Chang, Jonathan Chang, Dar Sun, Yu-Der Chih, Kerem Akarvardar, H. Mori and Chia-Fu Lee. Their work appears in journals such as IEEE Journal of Solid-State Circuits, 2022 IEEE International Solid- State Circuits Conference (ISSCC), IEICE technical report. Speech and IEEE Conference Proceedings.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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