Chieh-Pu Lo

1.1k citations

18 papers · 750 · 1 hit paper · h-index 12

Impact in

Hardware and Architecture top 5%
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Energy Harvesting in Wireless Networks
- CCD and CMOS Imaging Sensors

Papers in

Electrical and Electronic Engineering 15
- Ferroelectric and Negative Capacitance Devices 12
- Advanced Memory and Neural Computing 11
- Energy Harvesting in Wireless Networks 4
- Semiconductor materials and devices 4
- VLSI and FPGA Design Techniques 1
Computer Networks and Communications 5
- Advanced Data Storage Technologies 2

Co-authors: Meng‐Fan Chang (11 shared papers)Yu-Der Chih (7 shared papers)Yi-Chun Shih (5 shared papers)Chia-Fu Lee (4 shared papers)Po-Hao Lee (4 shared papers)Tsung-Yung Jonathan Chang (4 shared papers)Ya‐Chin King (7 shared papers)Fang Su (6 shared papers)
Journals: IEEE Journal of Solid-State Circuits (4 papers)Rare & Special e-Zone (The Hong Kong University of Science and Technology) (1 paper)
Partner nations: Taiwan United States China

In The Last Decade

Chieh-Pu Lo

18 papers receiving 735 citations

Chieh-Pu Lo's Hit Papers

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16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications 2021 · 231 citations

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if any of the following hold:

it has ≥500 total citations;
it reaches ≥1.5× the top-1% citation threshold for papers in the same subfield and year (the threshold is the minimum needed to enter the top 1%, not the average within it);
it reaches the top citation threshold in at least one of its specific research topics.

2021 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Peers

Countries citing papers authored by Chieh-Pu Lo

Since Specialization

Citations

This map shows the geographic impact of Chieh-Pu Lo's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chieh-Pu Lo with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chieh-Pu Lo more than expected).

Fields of papers citing papers by Chieh-Pu Lo

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chieh-Pu Lo. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chieh-Pu Lo. The network helps show where Chieh-Pu Lo may publish in the future.

Co-authors

The 25 scholars most cited alongside Chieh-Pu Lo, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Chieh-Pu Lo Line = papers co-authored together Chieh-Pu Lo links everyone, so they are left out of the graph.

All Works

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18 of 18 papers shown

#	Work
1	16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yulin Chen, Chieh-Pu Lo, C.W. Lu, H. Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan‐Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng‐Fan Chang, Tsung-Yung Jonathan Chang Hit paper breakdown →	2021	231
2	4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya‐Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng‐Fan Chang, Huazhong Yang	2016	85
3	13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yulin Chen, Chieh-Pu Lo, Meng-Chun Shih, Kuei‐Hung Shen, Harry Chuang, Tsung-Yung Jonathan Chang	2020	71
4	7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya‐Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng‐Fan Chang	2016	61
5	A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory Fang Su, Wei-Hao Chen, Lixue Xia, Chieh-Pu Lo, Tianqi Tang, Zhibo Wang, Kuo-Hsiang Hsu, Ming Cheng, Junyi Li, Yuan Xie, Yu Wang, Meng‐Fan Chang, Huazhong Yang, Yongpan Liu	2017	54
6	A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors IEEE Journal of Solid-State Circuits ·Albert Lee, Chieh-Pu Lo, Chien-Chen Lin, Wei-Hao Chen, Kuo-Hsiang Hsu, Zhibo Wang, Fang Su, Zhe Yuan, Qi Wei, Ya‐Chin King, Chrong-Jung Lin, Hochul Lee, Pedram Khalili Amiri, Kang-Lung Wang, Yu Wang, Huazhong Yang, Yongpan Liu, Meng‐Fan Chang	2017	45
7	A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory Rare & Special e-Zone (The Hong Kong University of Science and Technology) ·Fang Su, Wei-Hao Chen, Lixue Xia, Chieh-Pu Lo, Tianqi Tang, Zhibo Wang, Kuo-Hsiang Hsu, Ming Cheng, Junyi Li, Yuan Xie, Yu Wang, Meng‐Fan Chang, Huazhong Yang, Yongpan Liu	2017	40
8	A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yulin Chen, Chieh-Pu Lo, Ku-Feng Lin, Tien-Wei Chiang, Yuan-Jen Lee, Kuei‐Hung Shen, (unknown), Wayne Wang, Harry Chuang, Eric W. Wang, Yu-Der Chih, Jonathan Chang	2020	36
9	33.1 A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, C.W. Lu, Yulin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng‐Hsiung Kuo, Tan‐Li Chou, Chia-Yu Wang, J. J. Wu, (unknown), Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang	2023	34
10	A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Fang Su, Ya‐Chin King, Chrong Jung Lin, Yongpan Liu, Huazhong Yang, Pedram Khalili Amiri, Kang-Lung Wang, Meng‐Fan Chang	2016	22
11	Embedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications Chieh-Pu Lo, Wen-Zhang Lin, Wei‐Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya‐Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Mon‐Shu Ho, Meng‐Fan Chang	2017	18
12	A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation IEEE Journal of Solid-State Circuits ·Chieh-Pu Lo, Wen-Zhang Lin, Wei‐Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya‐Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Meng‐Fan Chang	2019	16
13	A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device IEEE Journal of Solid-State Circuits ·Yen-Cheng Chiu, Tung-Cheng Chang, Chun‐Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, H. Y. Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng‐Fan Chang	2021	10
14	A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving $> 4\times $ Faster Clock Frequency and $> 6\times $ Higher Restore Speed IEEE Journal of Solid-State Circuits ·Zhibo Wang, Yongpan Liu, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya‐Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng‐Fan Chang, Huazhong Yang	2017	9
15	30.6 Vecim: A 289.13GOPS/W RISC-V Vector Co-Processor with Compute-in-Memory Vector Register File for Efficient High-Performance Computing Yipeng Wang, Mengtian Yang, Chieh-Pu Lo, Jaydeep P. Kulkarni	2024	8
16	CMOS-MEMS Capacitive Humidity Sensor Nathan Lazarus, Sarah S. Bedair, Chieh-Pu Lo, Gary K. Fedder	2009	6
17	CILP: An Arbitrary-bit Precision All-digital Compute-in-memory Solver for Integer Linear Programming Problems Mengtian Yang, Yipeng Wang, Shanshan Xie, Chieh-Pu Lo, Meizhi Wang, Sirish Oruganti, Rishabh Sehgal, Jaydeep P. Kulkarni	2024	2
18	Data Movement-Aware, Ping-Pong Ising Machine Supporting Full Connectivity and Variable Bitwidths Chieh-Pu Lo, Sirish Oruganti, Yipeng Wang, Mengtian Yang, Shanshan Xie, Jaydeep P. Kulkarni	2024	2

About Chieh-Pu Lo

Chieh-Pu Lo is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications, Hardware and Architecture, Atomic and Molecular Physics, and Optics and Artificial Intelligence, having authored 18 papers that have together received 750 indexed citations. Recurring topics across this work include Ferroelectric and Negative Capacitance Devices (12 papers), Advanced Memory and Neural Computing (11 papers), Energy Harvesting in Wireless Networks (4 papers), Semiconductor materials and devices (4 papers), Parallel Computing and Optimization Techniques (3 papers), Magnetic properties of thin films (3 papers), Advanced Data Storage Technologies (2 papers) and VLSI and FPGA Design Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (153 citations), Electrical and Electronic Engineering (666 citations), Computer Networks and Communications (78 citations), Artificial Intelligence (92 citations) and Atomic and Molecular Physics, and Optics (71 citations). Chieh-Pu Lo has collaborated with scholars based in Taiwan, United States and China. Frequent co-authors include Meng‐Fan Chang, Yu-Der Chih, Yi-Chun Shih, Chia-Fu Lee, Po-Hao Lee, Tsung-Yung Jonathan Chang, Ya‐Chin King, Fang Su, Yongpan Liu and Huazhong Yang. Their work appears in journals such as IEEE Journal of Solid-State Circuits and Rare & Special e-Zone (The Hong Kong University of Science and Technology).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Chieh-Pu Lo

Chieh-Pu Lo's Hit Papers

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Fields of papers citing papers by Chieh-Pu Lo

All Works

About Chieh-Pu Lo

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