Xiaoxin Cui

917 citations

134 papers · 577 · h-index 11

Impact in

Hardware and Architecture top 5%
Electrical and Electronic Engineering top 10%
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design

Papers in

Electrical and Electronic Engineering 109
- Advanced Memory and Neural Computing 73
- Ferroelectric and Negative Capacitance Devices 46
- Semiconductor materials and devices 22
- Advancements in Semiconductor Devices and Circuit Design 13
Artificial Intelligence 37
- Neural Networks and Reservoir Computing 12

Co-authors: Xiaole Cui (50 shared papers)Dunshan Yu (41 shared papers)Yuan Wang (39 shared papers)Kefei Liu (17 shared papers)Ru Huang (8 shared papers)Kai Liao (12 shared papers)Kaisheng Ma (7 shared papers)Yi Zhong (10 shared papers)
Journals: IEEE Transactions on Circuits & Systems II Express Briefs (8 papers)Science China Information Sciences (7 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (3 papers)IEEE Journal of the Electron Devices Society (3 papers)Frontiers in Neuroscience (3 papers)
Partner nations: China United States Singapore

In The Last Decade

Xiaoxin Cui

118 papers receiving 561 citations

Peers

Countries citing papers authored by Xiaoxin Cui

Since Specialization

Citations

This map shows the geographic impact of Xiaoxin Cui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xiaoxin Cui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xiaoxin Cui more than expected).

Fields of papers citing papers by Xiaoxin Cui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xiaoxin Cui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xiaoxin Cui. The network helps show where Xiaoxin Cui may publish in the future.

Co-authors

The 25 scholars most cited alongside Xiaoxin Cui, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Xiaoxin Cui Line = papers co-authored together Xiaoxin Cui links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 134 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS IEEE Transactions on Circuits & Systems II Express Briefs ·Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang	2021	43
2	Low power adiabatic logic based on FinFETs Science China Information Sciences ·Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu	2014	33
3	A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling IEEE Transactions on Circuits & Systems II Express Briefs ·Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang	2022	21
4	An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin	2017	21
5	Toward High-Accuracy and Low-Latency Spiking Neural Networks With Two-Stage Optimization IEEE Transactions on Neural Networks and Learning Systems ·Ziming Wang, Yuhao Zhang, Shuang Lian, Xiaoxin Cui, Rui Yan, Huajin Tang	2023	17
6	A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation IEEE Transactions on Circuits & Systems II Express Briefs ·Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin’an Wang, Yuan Wang	2023	14
7	A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model Frontiers in Neuroscience ·Kefei Liu, Xiaoxin Cui, Yi Zhong, Yisong Kuang, Yuan Wang, Huajin Tang, Ru Huang	2019	13
8	ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang	2022	13
9	A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang	2021	12
10	LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion Remote Sensing ·Kunyu Feng, Lun Li, Xiaofeng Wang, Xiaoxin Cui	2023	12
11	Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array IEEE Journal of the Electron Devices Society ·Xiaole Cui, Miaomiao Zhang, Qiujun Lin, Xiaoxin Cui, Anqi Pang	2019	12
12	A New Scheme of the Low-Cost Multiple-Node-Upset-Tolerant Latch IEEE Transactions on Device and Materials Reliability ·Xiaole Cui, Qixue Zhang, Xiaoxin Cui	2022	10
13	A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu	2013	10
14	PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm IEEE Journal of Solid-State Circuits ·Yi Zhong, Yisong Kuang, Kefei Liu, Zilin Wang, Shuo Feng, Guang Chen, Youming Yang, Xiuping Cui, Q.J. Wang, Jian Cao, Song Jia, Yun Liang, Guangyu Sun, Xiaoxin Cui, Ru Huang, Yuan Wang	2024	9
15	Improving DFA attacks on AES with unknown and random faults Science China Information Sciences ·Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui	2016	9
16	BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, YiHsiang Chen, Rongshan Wei	2019	9
17	An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning IEEE Transactions on Circuits & Systems II Express Briefs ·Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang	2023	9
18	Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs Science China Information Sciences ·Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu	2014	9
19	Polymorphic gate based IC watermarking techniques Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui	2018	9
20	The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates IEEE Access ·Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui	2020	8

About Xiaoxin Cui

Xiaoxin Cui is a scholar working on Electrical and Electronic Engineering, Artificial Intelligence, Hardware and Architecture, Cellular and Molecular Neuroscience and Cognitive Neuroscience, having authored 134 papers that have together received 577 indexed citations. Recurring topics across this work include Advanced Memory and Neural Computing (73 papers), Ferroelectric and Negative Capacitance Devices (46 papers), Semiconductor materials and devices (22 papers), Physical Unclonable Functions (PUFs) and Hardware Security (22 papers), Neural dynamics and brain function (22 papers), Neuroscience and Neural Engineering (21 papers), Advancements in Semiconductor Devices and Circuit Design (13 papers) and Neural Networks and Reservoir Computing (12 papers). The work is most often cited by research in Hardware and Architecture (106 citations), Electrical and Electronic Engineering (473 citations), Cellular and Molecular Neuroscience (87 citations), Artificial Intelligence (134 citations) and Cognitive Neuroscience (78 citations). Xiaoxin Cui has collaborated with scholars based in China, United States and Singapore. Frequent co-authors include Xiaole Cui, Dunshan Yu, Yuan Wang, Kefei Liu, Ru Huang, Kai Liao, Kaisheng Ma, Yi Zhong, Xin’an Wang and Zhenhui Dai. Their work appears in journals such as IEEE Transactions on Circuits & Systems II Express Briefs, Science China Information Sciences, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Journal of the Electron Devices Society and Frontiers in Neuroscience.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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