Xiaoxin Cui

1.1k citations

143 papers · 745 · h-index 13

Impact in

Hardware and Architecture top 5%
- Physical Unclonable Functions (PUFs) and Hardware Security
- Embedded Systems Design Techniques
Electrical and Electronic Engineering top 5%
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Radiation Effects in Electronics

Papers in

Electrical and Electronic Engineering 102
- Advanced Memory and Neural Computing 67
- Low-power high-performance VLSI design 17
- Embedded Systems and FPGA Applications 7
- Advanced Wireless Communication Techniques 7
Hardware and Architecture 21
- Physical Unclonable Functions (PUFs) and Hardware Security 12
- VLSI and Analog Circuit Testing 5

Co-authors: Xiaole Cui (50 shared papers)Dunshan Yu (45 shared papers)Yuan Wang (42 shared papers)Kefei Liu (17 shared papers)Ru Huang (9 shared papers)Yi Zhong (10 shared papers)Kaisheng Ma (7 shared papers)Xin’an Wang (13 shared papers)
Journals: IEEE Transactions on Circuits & Systems II Express Briefs (8 papers)Science China Information Sciences (7 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (4 papers)IEEE Journal of the Electron Devices Society (3 papers)Frontiers in Neuroscience (3 papers)
Partner nations: China United States

In The Last Decade

Xiaoxin Cui

130 papers receiving 730 citations

Peers

Countries citing papers authored by Xiaoxin Cui

Since Specialization

Citations

This map shows the geographic impact of Xiaoxin Cui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xiaoxin Cui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xiaoxin Cui more than expected).

Fields of papers citing papers by Xiaoxin Cui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xiaoxin Cui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xiaoxin Cui. The network helps show where Xiaoxin Cui may publish in the future.

Co-authors

The 25 scholars most cited alongside Xiaoxin Cui, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Xiaoxin Cui Line = papers co-authored together Xiaoxin Cui links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 143 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS IEEE Transactions on Circuits & Systems II Express Briefs ·Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Yuan Wang, Dunshan Yu, Ru Huang +1 other	2021	49
2	Low power adiabatic logic based on FinFETs Science China Information Sciences ·Nan Liao, Xiaoxin Cui, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu +1 other	2014	39
3	Toward High-Accuracy and Low-Latency Spiking Neural Networks With Two-Stage Optimization IEEE Transactions on Neural Networks and Learning Systems ·Ziming Wang, Yuhao Zhang, Shuang Shii Lian, Xiaoxin Cui, Rui Yan, Huajin Tang	2023	32
4	An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao +1 other	2017	24
5	A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling IEEE Transactions on Circuits & Systems II Express Briefs ·Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang	2022	24
6	PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm IEEE Journal of Solid-State Circuits ·Yi Zhong, Yisong Kuang, Kefei Liu, Zilin Wang, Shuo Feng, Guang Chen, Youming Yang, Xiuping Cui	2024	21
7	ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Dunshan Yu, Yuan Wang	2022	19
8	A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS IEEE International Symposium on Circuits and Systems proceedings ·Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang	2021	18
9	LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion Remote Sensing ·Kunyu Feng, Lun Li, Xiaofeng Wang, Xiaoxin Cui	2023	17
10	A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation IEEE Transactions on Circuits & Systems II Express Briefs ·Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin’an Wang, Yuan Wang	2023	16
11	Improving DFA attacks on AES with unknown and random faults Science China Information Sciences ·Nan Liao, Xiaoxin Cui, Dunshan Yu, Xiaole Cui +2 others	2016	13
12	A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model Frontiers in Neuroscience ·Kefei Liu, Xiaoxin Cui, Yi Fang Zhong, Yisong Kuang, Yuan Wang, Huajin Tang, Ru Huang	2019	13
13	Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array IEEE Journal of the Electron Devices Society ·Xiaole Cui, Miaomiao Zhang, Qiujun Lin, Xiaoxin Cui +1 other	2019	13
14	A hybrid fault model for differential fault attack on AES IEEE International Conference on ASIC (ASICON) ·Yixia Liu, Xiaoxin Cui, Jian Cao, Xing Zhang	2017	12
15	A New Scheme of the Low-Cost Multiple-Node-Upset-Tolerant Latch IEEE Transactions on Device and Materials Reliability ·Xiaole Cui, Qixue Zhang, Xiaoxin Cui	2022	12
16	An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning IEEE Transactions on Circuits & Systems II Express Briefs ·Yi Zhong, Zilin Wang, Xiaoxin Cui, Yuan Wang +1 other	2023	12
17	A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs IEEE International Symposium on Circuits and Systems proceedings ·Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Dunshan Yu +2 others	2013	11
18	Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs Science China Information Sciences ·Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu +1 other	2014	11
19	Polymorphic gate based IC watermarking techniques Asia and South Pacific Design Automation Conference (ASP-DAC) ·Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui	2018	11
20	An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs IEEE Transactions on Information Forensics and Security ·Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui	2023	11

About Xiaoxin Cui

Xiaoxin Cui is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Artificial Intelligence, Computer Vision and Pattern Recognition and Signal Processing, having authored 143 papers that have together received 745 indexed citations. Recurring topics across this work include Advanced Memory and Neural Computing (67 papers), Low-power high-performance VLSI design (17 papers), Physical Unclonable Functions (PUFs) and Hardware Security (12 papers), Cryptographic Implementations and Security (9 papers), Advanced Neural Network Applications (8 papers), Embedded Systems and FPGA Applications (7 papers), Advanced Wireless Communication Techniques (7 papers) and VLSI and Analog Circuit Testing (5 papers). The work is most often cited by research in Hardware and Architecture (96 citations), Electrical and Electronic Engineering (545 citations), Computer Vision and Pattern Recognition (59 citations), Artificial Intelligence (70 citations) and Signal Processing (12 citations). Xiaoxin Cui has collaborated with scholars based in China and United States. Frequent co-authors include Xiaole Cui, Dunshan Yu, Yuan Wang, Kefei Liu, Ru Huang, Yi Zhong, Kaisheng Ma, Xin’an Wang, Rui Li and Huajin Tang. Their work appears in journals such as IEEE Transactions on Circuits & Systems II Express Briefs, Science China Information Sciences, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Journal of the Electron Devices Society and Frontiers in Neuroscience.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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