V. Dabholkar
Impact in
- Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing
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- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Photolithography Techniques
- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- Radiation Effects in Electronics
- Advancements in Semiconductor Devices and Circuit Design
Papers in
-
- VLSI and Analog Circuit Testing 6
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- Integrated Circuits and Semiconductor Failure Analysis 5
- Semiconductor materials and devices 2
- Advancements in Photolithography Techniques 2
- VLSI and FPGA Design Techniques 1
- Co-authors
- Irith Pomeranz (1 shared paper)S. Chakravarty (1 shared paper)S.M. Reddy (1 shared paper)S. Chakravarty (5 shared papers)Sreejit Chakravarty (1 shared paper)
- Partner nations
- United States
In The Last Decade
V. Dabholkar
7 papers receiving 307 citations
Peers
Comparison fields: 5 of 9
- Hardware and Architecture 333
- Electrical and Electronic Engineering 332
- Control and Systems Engineering 48
- Industrial and Manufacturing Engineering 2
- Computational Theory and Mathematics 2
Countries citing papers authored by V. Dabholkar
This map shows the geographic impact of V. Dabholkar's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Dabholkar with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Dabholkar more than expected).
Fields of papers citing papers by V. Dabholkar
This network shows the impact of papers produced by V. Dabholkar. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Dabholkar. The network helps show where V. Dabholkar may publish in the future.
Co-authors
The 5 scholars most cited alongside V. Dabholkar, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 1998 | 261 | |
| 2 | 2002 | 56 | |
| 3 | Minimizing Power Dissipation in Scan Circuits During Test Application | 1994 | 7 |
| 4 | 1995 | 5 | |
| 5 | Optimization problems in low power and stress testing | 1996 | 4 |
| 6 | 2002 | 1 | |
| 7 | 2002 | 1 |
About V. Dabholkar
V. Dabholkar is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, General Health Professions, Philosophy and Biomedical Engineering, having authored 7 papers that have together received 335 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (6 papers), Integrated Circuits and Semiconductor Failure Analysis (5 papers), Semiconductor materials and devices (2 papers), Advancements in Photolithography Techniques (2 papers), Advanced Surface Polishing Techniques (1 paper), Hermeneutics and Narrative Identity (1 paper), Health, Medicine and Society (1 paper) and VLSI and FPGA Design Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (333 citations), Electrical and Electronic Engineering (332 citations), Control and Systems Engineering (48 citations), Industrial and Manufacturing Engineering (2 citations) and Computational Theory and Mathematics (2 citations). V. Dabholkar has collaborated with scholars based in United States. Frequent co-authors include Irith Pomeranz, S. Chakravarty, S.M. Reddy, S. Chakravarty and Sreejit Chakravarty. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.