Eddie Hung

477 citations

28 papers · 311 · h-index 11

Impact in

Hardware and Architecture top 2%
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering
- VLSI and FPGA Design Techniques
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- Integrated Circuits and Semiconductor Failure Analysis

Papers in

Hardware and Architecture 24
- VLSI and Analog Circuit Testing 15
- Embedded Systems Design Techniques 9
- Parallel Computing and Optimization Techniques 5
- Physical Unclonable Functions (PUFs) and Hardware Security 3
Electrical and Electronic Engineering 24
- VLSI and FPGA Design Techniques 16
- Low-power high-performance VLSI design 13
- Radiation Effects in Electronics 4
- Integrated Circuits and Semiconductor Failure Analysis 3

Co-authors: Steven J. E. Wilton (12 shared papers)Wayne Luk (5 shared papers)Jose Nunez‐Yanez (2 shared papers)Thomas Chau (1 shared paper)Philip H. W. Leong (1 shared paper)Tim Todman (2 shared papers)Edward Stott (5 shared papers)Joshua M. Levine (5 shared papers)
Journals: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (3 papers)ACM Transactions on Reconfigurable Technology and Systems (2 papers)IEEE Design and Test (2 papers)ACM Transactions on Design Automation of Electronic Systems (1 paper)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)
Partner nations: Canada United Kingdom United States

In The Last Decade

Eddie Hung

27 papers receiving 307 citations

Peers

Countries citing papers authored by Eddie Hung

Since Specialization

Citations

This map shows the geographic impact of Eddie Hung's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Eddie Hung with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Eddie Hung more than expected).

Fields of papers citing papers by Eddie Hung

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Eddie Hung. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Eddie Hung. The network helps show where Eddie Hung may publish in the future.

Co-authors

The 25 scholars most cited alongside Eddie Hung, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Eddie Hung Line = papers co-authored together Eddie Hung links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 28 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton	2013	32
2	Accelerating SpMV on FPGAs by Compressing Nonzero Values Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk	2015	29
3	Scalable Signal Selection for Post-Silicon Debug IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Eddie Hung, Steven J. E. Wilton	2012	27
4	A detailed delay path model for FPGAs Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas Chau, Philip H. W. Leong	2009	27
5	Incremental Trace-Buffer Insertion for FPGA Debug IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Eddie Hung, Steven J. E. Wilton	2013	26
6	Towards simulator-like observability for FPGAs Eddie Hung, Steven J. E. Wilton	2013	23
7	Speculative Debug Insertion for FPGAs Eddie Hung, Steven J. E. Wilton	2011	19
8	Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Jose Nunez‐Yanez, Atukem Nabina, Eddie Hung, George Vafiadis	2011	17
9	Limitations of incremental signal-tracing for FPGA debug Eddie Hung, Steven J. E. Wilton	2012	14
10	Transparent insertion of latency-oblivious logic onto FPGAs Eddie Hung, Tim Todman, Wayne Luk	2014	14
11	On evaluating signal selection algorithms for post-silicon debug Eddie Hung, Steven J. E. Wilton	2011	11
12	A configurable and programmable motion estimation processor for the H.264 video codec Bristol Research (University of Bristol) ·Jose Nunez‐Yanez, Eddie Hung, Vassilios Chouliaras	2008	10
13	KAPow ACM Transactions on Reconfigurable Technology and Systems ·James J. Davis, Eddie Hung, Joshua M. Levine, Edward Stott, Peter Y. K. Cheung, George A. Constantinides	2018	9
14	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs Spiral (Imperial College London) ·Eddie Hung, James J. Davis, Joshua M. Levine, Edward Stott, Peter Y. K. Cheung, George A. Constantinides	2016	9
15	Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry Eddie Hung	2015	8
16	Maximum flow algorithms for maximum observability during FPGA debug Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton	2013	7
17	RapidStream 2.0: Automated Parallel Implementation of Latency–Insensitive FPGA Designs Through Partial Reconfiguration ACM Transactions on Reconfigurable Technology and Systems ·Licheng Guo, Pongstorn Maidee, Yun Zhou, Christopher Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong	2023	5
18	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry Benjamin L.C. Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan Greene, John Wawrzynek	2023	5
19	STRIPE: Signal selection for runtime power estimation Spiral (Imperial College London) ·James J. Davis, Joshua M. Levine, Edward Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides	2017	4
20	EFCAD — An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation Research Explorer (The University of Manchester) ·Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung	2019	3

About Eddie Hung

Eddie Hung is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computer Networks and Communications, Computer Vision and Pattern Recognition and Signal Processing, having authored 28 papers that have together received 311 indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (16 papers), VLSI and Analog Circuit Testing (15 papers), Low-power high-performance VLSI design (13 papers), Embedded Systems Design Techniques (9 papers), Parallel Computing and Optimization Techniques (5 papers), Radiation Effects in Electronics (4 papers), Physical Unclonable Functions (PUFs) and Hardware Security (3 papers) and Integrated Circuits and Semiconductor Failure Analysis (3 papers). The work is most often cited by research in Hardware and Architecture (258 citations), Electrical and Electronic Engineering (227 citations), Computer Networks and Communications (48 citations), Computer Vision and Pattern Recognition (37 citations) and Signal Processing (18 citations). Eddie Hung has collaborated with scholars based in Canada, United Kingdom and United States. Frequent co-authors include Steven J. E. Wilton, Wayne Luk, Jose Nunez‐Yanez, Thomas Chau, Philip H. W. Leong, Tim Todman, Edward Stott, Joshua M. Levine, George A. Constantinides and Peter Y. K. Cheung. Their work appears in journals such as IEEE Transactions on Very Large Scale Integration (VLSI) Systems, ACM Transactions on Reconfigurable Technology and Systems, IEEE Design and Test, ACM Transactions on Design Automation of Electronic Systems and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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