Debesh K. Das

874 citations

103 papers · 525 · h-index 12

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
Computational Theory and Mathematics top 5%
- Quantum-Dot Cellular Automata

Papers in

Electrical and Electronic Engineering 82
- Low-power high-performance VLSI design 39
- Integrated Circuits and Semiconductor Failure Analysis 31
- Radiation Effects in Electronics 17
- VLSI and FPGA Design Techniques 17
Hardware and Architecture 52
- VLSI and Analog Circuit Testing 52

Co-authors: Bhargab B. Bhattacharya (41 shared papers)Hafizur Rahaman (35 shared papers)Nur A. Touba (2 shared papers)Dipak Kumar Kole (14 shared papers)Arindam Banerjee (8 shared papers)Michael Gössel (1 shared paper)Susanta Chakraborty (7 shared papers)Biplab K. Sikdar (8 shared papers)
Journals: Computers & Electrical Engineering (3 papers)ACM Journal on Emerging Technologies in Computing Systems (2 papers)Analog Integrated Circuits and Signal Processing (2 papers)Multimedia Tools and Applications (1 paper)Sadhana (1 paper)
Partner nations: India United States Japan

In The Last Decade

Debesh K. Das

93 papers receiving 477 citations

Peers

Countries citing papers authored by Debesh K. Das

Since Specialization

Citations

This map shows the geographic impact of Debesh K. Das's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Debesh K. Das with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Debesh K. Das more than expected).

Fields of papers citing papers by Debesh K. Das

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Debesh K. Das. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Debesh K. Das. The network helps show where Debesh K. Das may publish in the future.

Co-authors

The 25 scholars most cited alongside Debesh K. Das, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Debesh K. Das Line = papers co-authored together Debesh K. Das links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 103 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Weight-based codes and their application to concurrent error detection of multilevel circuits Debesh K. Das, Nur A. Touba	2003	59
2	Low cost concurrent error detection based on module weight-based codes Debesh K. Das, Nur A. Touba, M. Seuring, Michael Gössel	2002	45
3	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya	2008	33
4	Fault diagnosis in reversible circuits under missing-gate fault model Computers & Electrical Engineering ·Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya	2011	22
5	Optimum Test Set for Bridging Fault Detection in Reversible Circuits Hafizur Rahaman, Dipak Kumar Kole, Debesh K. Das, Bhargab B. Bhattacharya	2007	21
6	Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method Bappaditya Mondal, Dipak Kumar Kole, Debesh K. Das, Hafizur Rahaman	2014	16
7	Synthesis of symmetric functions for path-delay fault testability IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·S. Chakrabarti, Swagatam Das, Debesh K. Das, Bhargab B. Bhattacharya	2000	14
8	Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2010	13
9	Design of an optimal test pattern generator for built-in self testing of path delay faults Debesh K. Das, I. Chaudhuri, Bhargab B. Bhattacharya	2002	13
10	Testable design of non-scan sequential circuits using extra logic Debesh K. Das, Bhargab B. Bhattacharya	2002	13
11	Notice of Removal: Synthesis of online testable reversible circuit Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2010	13
12	Testable design of AND–EXOR logic networks with universal test sets Computers & Electrical Engineering ·Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2009	11
13	Easily testable realization of GRM and ESOP networks for detecting stuck-at and bridging faults Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2004	10
14	Delay Estimates for Graphene Nanoribbons Subrata Das, Soma Das, Majumder Adrija, Parthasarathi Dasgupta, Debesh K. Das	2016	9
15	A New Squarer design with reduced area and delay IET Computers & Digital Techniques ·Arindam Banerjee, Debesh K. Das	2016	8
16	A technique to construct global routing trees for graphene nanoribbon (GNR) Subrata Das, Debesh K. Das	2017	8
17	Transition count based BIST for detecting multiple stuck-open faults in CMOS circuits Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2002	8
18	Testing of stuck-open faults in generalised Reed–Muller and EXOR sum-of-products CMOS circuits IEE Proceedings - Computers and Digital Techniques ·Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2004	8
19	IRUVD: a new still-image based dataset for automatic vehicle detection Multimedia Tools and Applications ·Asfak Ali, Ram Sarkar, Debesh K. Das	2023	7
20	Derivation of test set for detecting multiple missing-gate faults in reversible circuits Computers & Electrical Engineering ·Dipak Kumar Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya	2012	7

About Debesh K. Das

Debesh K. Das is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computational Theory and Mathematics, Artificial Intelligence and Materials Chemistry, having authored 103 papers that have together received 525 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (52 papers), Low-power high-performance VLSI design (39 papers), Integrated Circuits and Semiconductor Failure Analysis (31 papers), Quantum Computing Algorithms and Architecture (27 papers), Quantum-Dot Cellular Automata (24 papers), Radiation Effects in Electronics (17 papers), VLSI and FPGA Design Techniques (17 papers) and Quantum Information and Cryptography (13 papers). The work is most often cited by research in Hardware and Architecture (217 citations), Computational Theory and Mathematics (149 citations), Artificial Intelligence (223 citations), Electrical and Electronic Engineering (375 citations) and Software (11 citations). Debesh K. Das has collaborated with scholars based in India, United States and Japan. Frequent co-authors include Bhargab B. Bhattacharya, Hafizur Rahaman, Nur A. Touba, Dipak Kumar Kole, Arindam Banerjee, Michael Gössel, Susanta Chakraborty, Biplab K. Sikdar, Swagatam Das and Chandan Giri. Their work appears in journals such as Computers & Electrical Engineering, ACM Journal on Emerging Technologies in Computing Systems, Analog Integrated Circuits and Signal Processing, Multimedia Tools and Applications and Sadhana.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Debesh K. Das

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