Ben Keller

1.4k citations

28 papers · 941 · h-index 16

Impact in

Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
Computational Mathematics top 10%

Papers in

Electrical and Electronic Engineering 25
- Low-power high-performance VLSI design 15
- Advanced Memory and Neural Computing 7
- VLSI and FPGA Design Techniques 5
- Ferroelectric and Negative Capacitance Devices 5
Hardware and Architecture 13
- Parallel Computing and Optimization Techniques 8
- VLSI and Analog Circuit Testing 4

Co-authors: Brucek Khailany (17 shared papers)Brian Zimmer (16 shared papers)William J. Dally (10 shared papers)Rangharajan Venkatesan (9 shared papers)Yanqing Zhang (10 shared papers)Matthew Fojtik (8 shared papers)Alicia Klinefelter (8 shared papers)Stephen G. Tell (8 shared papers)
Journals: IEEE Journal of Solid-State Circuits (4 papers)IEEE Micro (2 papers)IEEE Solid-State Circuits Letters (2 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)Communications of the ACM (1 paper)
Partner nations: United States France United Kingdom

In The Last Decade

Ben Keller

27 papers receiving 915 citations

Peers

Countries citing papers authored by Ben Keller

Since Specialization

Citations

This map shows the geographic impact of Ben Keller's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ben Keller with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ben Keller more than expected).

Fields of papers citing papers by Ben Keller

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ben Keller. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ben Keller. The network helps show where Ben Keller may publish in the future.

Co-authors

The 25 scholars most cited alongside Ben Keller, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Ben Keller Line = papers co-authored together Ben Keller links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Showing the 20 most-cited of 28 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Simba Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler	2019	248
2	MAGNet: A Modular Accelerator Generator for Neural Networks Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel Emer, Stephen W. Keckler, Brucek Khailany	2019	84
3	A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm IEEE Journal of Solid-State Circuits ·Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany	2020	82
4	An Agile Approach to Building RISC-V Microprocessors IEEE Micro ·Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtić, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Rimas Avižienis, Brian Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Borivoje Nikolić, Krste Asanović	2016	70
5	A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI IEEE Journal of Solid-State Circuits ·Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtić, Ben Keller, Steven Bailey, Milovan Blagojević, Pi-Feng Chiu, Hanh‐Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avižienis, Andrew Waterman, Brian Richards, Philippe Flatresse, Elad Alon, Krste Asanović, Borivoje Nikolić	2016	51
6	PRIMAL Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang	2019	42
7	A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany	2019	40
8	Accelerating Chip Design With Machine Learning IEEE Micro ·Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert M. Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally	2020	36
9	A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI Milovan Blagojević, Martin Cochet, Ben Keller, Philippe Flatresse, Andrei Vladimirescu, Borivoje Nikolić	2016	35
10	A 225 μm ${}^{2}$ Probe Single-Point Calibration Digital Temperature Sensor Using Body-Bias Adjustment in 28 nm FD-SOI CMOS IEEE Solid-State Circuits Letters ·Martin Cochet, Ben Keller, Sylvain Clerc, Fady Abouzeid, Andreia Cathelin, Jean‐Luc Autran, Philippe Roché, Borivoje Nikolić	2018	32
11	A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm IEEE Journal of Solid-State Circuits ·Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany	2023	30
12	A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany	2022	27
13	AutoDMP Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing Ren	2023	26
14	A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI IEEE Journal of Solid-State Circuits ·Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, Milovan Blagojević, Stevo Bailey, Pi-Feng Chiu, Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanović, Borivoje Nikolić	2017	26
15	A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtić, Ben Keller, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Hanh‐Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avižienis, Andrew Waterman, Brian Richards, Philippe Flatresse, Elad Alon, Krste Asanović, Borivoje Nikolić	2015	25
16	A Pausible Bisynchronous FIFO for GALS Systems Ben Keller, Matthew Fojtik, Brucek Khailany	2015	18
17	Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojević, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanović, Borivoje Nikolić	2016	12
18	Simba Communications of the ACM ·Yakun Sophia Shao, Jason Cemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler	2021	11
19	A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany	2019	10
20	Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtić, Ben Keller, Stevo Bailey, Milovan Blagojević, Pi-Feng Chiu, Henry Cook, Rimas Avižienis, Brian Richards, Elad Alon, Borivoje Nikolić, Krste Asanović	2015	9

About Ben Keller

Ben Keller is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computer Vision and Pattern Recognition, Biomedical Engineering and Artificial Intelligence, having authored 28 papers that have together received 941 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (15 papers), Parallel Computing and Optimization Techniques (8 papers), Advanced Neural Network Applications (8 papers), Advanced Memory and Neural Computing (7 papers), Analog and Mixed-Signal Circuit Design (5 papers), VLSI and FPGA Design Techniques (5 papers), Ferroelectric and Negative Capacitance Devices (5 papers) and VLSI and Analog Circuit Testing (4 papers). The work is most often cited by research in Hardware and Architecture (385 citations), Computational Mathematics (14 citations), Electrical and Electronic Engineering (660 citations), Computer Vision and Pattern Recognition (232 citations) and Computer Networks and Communications (163 citations). Ben Keller has collaborated with scholars based in United States, France and United Kingdom. Frequent co-authors include Brucek Khailany, Brian Zimmer, William J. Dally, Rangharajan Venkatesan, Yanqing Zhang, Matthew Fojtik, Alicia Klinefelter, Stephen G. Tell, C. Thomas Gray and Nathaniel Pinckney. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Micro, IEEE Solid-State Circuits Letters, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Communications of the ACM.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

Ben Keller

Impact in

Papers in i

In The Last Decade

Ben Keller

Peers

Countries citing papers authored by Ben Keller

Fields of papers citing papers by Ben Keller

All Works

About Ben Keller

Explore authors with similar magnitude of impact

Papers in