Andrew Lines
Impact in
- Hardware and Architecture top 1%
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- VLSI and Analog Circuit Testing
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- Interconnection Networks and Systems
Papers in
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- Low-power high-performance VLSI design 12
- VLSI and FPGA Design Techniques 4
- Advanced Memory and Neural Computing 3
- Semiconductor materials and devices 2
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- Parallel Computing and Optimization Techniques 5
- VLSI and Analog Circuit Testing 3
- Embedded Systems Design Techniques 2
- Co-authors
- Peter A. Beerel (4 shared papers)Alain J. Martin (2 shared papers)Uri Cummings (2 shared papers)Paul Penzes (1 shared paper)Rajit Manohar (1 shared paper)M. Nystrom (1 shared paper)Georgios D. Dimou (3 shared papers)Michael Davies (1 shared paper)
- Journals
- IEEE Micro (1 paper)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)CaltechAUTHORS (California Institute of Technology) (1 paper)IEEE Design & Test of Computers (1 paper)
- Partner nations
- United StatesSwitzerlandUnited Kingdom
In The Last Decade
Andrew Lines
15 papers receiving 659 citations
Peers
Comparison fields: 5 of 26
- Hardware and Architecture 481
- Computer Networks and Communications 254
- Electrical and Electronic Engineering 587
- Computational Theory and Mathematics 109
- Artificial Intelligence 40
Countries citing papers authored by Andrew Lines
This map shows the geographic impact of Andrew Lines's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Andrew Lines with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Andrew Lines more than expected).
Fields of papers citing papers by Andrew Lines
This network shows the impact of papers produced by Andrew Lines. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Andrew Lines. The network helps show where Andrew Lines may publish in the future.
Co-authors
The 23 scholars most cited alongside Andrew Lines, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2002 | 213 | |
| 2 | 1998 | 164 | |
| 3 | 2004 | 81 | |
| 4 | 2011 | 66 | |
| 5 | 2006 | 66 | |
| 6 | 2018 | 27 | |
| 7 | 2002 | 22 | |
| 8 | 2004 | 20 | |
| 9 | 2014 | 15 | |
| 10 | 2009 | 13 | |
| 11 | 2007 | 5 | |
| 12 | 2013 | 5 | |
| 13 | 2018 | 3 | |
| 14 | 2014 | 2 | |
| 15 | 2021 | 2 | |
| 16 | 2025 | 0 |
About Andrew Lines
Andrew Lines is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Computer Networks and Communications, Cellular and Molecular Neuroscience and Signal Processing, having authored 16 papers that have together received 704 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (12 papers), Parallel Computing and Optimization Techniques (5 papers), Interconnection Networks and Systems (5 papers), VLSI and FPGA Design Techniques (4 papers), Advanced Memory and Neural Computing (3 papers), VLSI and Analog Circuit Testing (3 papers), Embedded Systems Design Techniques (2 papers) and Semiconductor materials and devices (2 papers). The work is most often cited by research in Hardware and Architecture (481 citations), Computer Networks and Communications (254 citations), Electrical and Electronic Engineering (587 citations), Computational Theory and Mathematics (109 citations) and Artificial Intelligence (40 citations). Andrew Lines has collaborated with scholars based in United States, Switzerland and United Kingdom. Frequent co-authors include Peter A. Beerel, Alain J. Martin, Uri Cummings, Paul Penzes, Rajit Manohar, M. Nystrom, Georgios D. Dimou, Michael Davies, Nam‐Hoon Kim and Jonathan Tse. Their work appears in journals such as IEEE Micro, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CaltechAUTHORS (California Institute of Technology) and IEEE Design & Test of Computers.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.