John Barth

760 citations

33 papers · 589 · h-index 13

Impact in

Hardware and Architecture top 2%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing

Papers in

Hardware and Architecture 13
- VLSI and Analog Circuit Testing 10
Electrical and Electronic Engineering 32
- Semiconductor materials and devices 19
- Low-power high-performance VLSI design 17
- Advancements in Semiconductor Devices and Circuit Design 14
- 3D IC and TSV technologies 4
- Integrated Circuits and Semiconductor Failure Analysis 4
- Advanced Memory and Neural Computing 4
- Electronic Packaging and Soldering Technologies 4

Co-authors: Subramanian S. Iyer (8 shared papers)Paul Parries (5 shared papers)Erik Nelson (7 shared papers)Toshiaki Kirihata (8 shared papers)William R. Reohr (6 shared papers)Charles H. Stapper (3 shared papers)Dennis Hoyniak (1 shared paper)Hillery C. Hunter (3 shared papers)
Journals: IEEE Journal of Solid-State Circuits (7 papers)IBM Journal of Research and Development (4 papers)Journal of Low Power Electronics and Applications (1 paper)Symposium on VLSI Technology (1 paper)Integrated circuits and systems (1 paper)
Partner nations: United States France Germany

In The Last Decade

John Barth

33 papers receiving 561 citations

Peers

Countries citing papers authored by John Barth

Since Specialization

Citations

This map shows the geographic impact of John Barth's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by John Barth with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites John Barth more than expected).

Fields of papers citing papers by John Barth

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by John Barth. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by John Barth. The network helps show where John Barth may publish in the future.

Co-authors

The 25 scholars most cited alongside John Barth, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with John Barth Line = papers co-authored together John Barth links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 33 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC IEEE Journal of Solid-State Circuits ·H.L. Kalter, Charles H. Stapper, John Barth, Jonathan DiLorenzo, C. Drake, J.A. Fifield, G.A. Kelley, Scott C. Lewis	1990	90
2	Processor-based built-in self-test for embedded DRAM IEEE Journal of Solid-State Circuits ·J. Dreibelbis, John Barth, H.L. Kalter, Rex Kho	1998	71
3	Embedded DRAM: Technology platform for the Blue Gene/L chip IBM Journal of Research and Development ·Subramanian S. Iyer, John Barth, Paul Parries, J. P. Norum, J. Rice, L. R. Logan, Dennis Hoyniak	2005	59
4	A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier IEEE Journal of Solid-State Circuits ·John Barth, William R. Reohr, Paul Parries, G. Fredeman, John W. Golz, Stanley E. Schuster, Richard E. Matick, Hillery C. Hunter	2008	50
5	A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache IEEE Journal of Solid-State Circuits ·John Barth, Kavita Nair, Nianzheng Cao, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling	2010	42
6	A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier John Barth, William R. Reohr, Paul Parries, G. Fredeman, John W. Golz, Stanley E. Schuster, Richard E. Matick, Hillery C. Hunter	2007	27
7	A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining IEEE Journal of Solid-State Circuits ·John Barth, Darren Anand, Steven M. Burns, J. Dreibelbis, J.A. Fifield, Kevin W. Gorman, M. Nelms, Erik Nelson	2005	23
8	Embedded DRAM built in self test and methodology for test insertion Peter Jul Jakobsen, J. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, M. Nelms, Janice Leach, G. Belansek	2002	21
9	An ASIC library granular DRAM macro with built-in self test J. Dreibelbis, John Barth, Rex Kho, T. Kalter	2002	19
10	Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering IBM Journal of Research and Development ·John Barth, J. Dreibelbis, Erik Nelson, Darren Anand, Gary Pomichter, Peter Jul Jakobsen, M. Nelms, Janice Leach	2002	18
11	Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology Journal of Low Power Electronics and Applications ·Pooja Batra, Spyridon Skordas, Douglas C. LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary W. Maier, Bishan He	2014	17
12	A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface IEEE Journal of Solid-State Circuits ·Harold Pilo, Darren Anand, John Barth, Steven M. Burns, Phillip L. Corson, J. Covino, S. Lamphier	2003	16
13	A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr	2010	14
14	A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS IEEE Journal of Solid-State Circuits ·Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien Nam Le, Aditya Khargonekar	2009	12
15	A 300MHz multi-banked, eDRAM macro featuring GND sense, bit-line twisting and direct reference cell write 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·John Barth, Darren Anand, J. Dreibelbis, Erik Nelson	2005	11
16	Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology Pooja Batra, Douglas C. LaTulipe, Spyridon Skordas, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary W. Maier, Bishan He	2013	11
17	A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications G. Wang, K. Cheng, H. Ho, Jonathan Faltermeier, Weiran Kong, H. Kim, J. Cai, Charles C. Tanner	2006	10
18	Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond Balaji Jayaraman, S.P. Gupta, Yanli Zhang, Puneet Goyal, Herbert L. Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee	2012	10
19	A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology Nauman Zafar Butt, Kevin Mcstay, Alberto Cestero, H. Ho, Weiran Kong, S. Fang, Rishikesh Krishnan, Bibi A Khan	2010	10
20	A 5.6 ns random cycle 144 Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface H. Pilo, Darren Anand, John Barth, Steven M. Burns, P. Corson, J. Covino, R. Houghton, S. Lamphier	2003	9

About John Barth

John Barth is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Automotive Engineering, Computer Networks and Communications and Biomedical Engineering, having authored 33 papers that have together received 589 indexed citations. Recurring topics across this work include Semiconductor materials and devices (19 papers), Low-power high-performance VLSI design (17 papers), Advancements in Semiconductor Devices and Circuit Design (14 papers), VLSI and Analog Circuit Testing (10 papers), 3D IC and TSV technologies (4 papers), Integrated Circuits and Semiconductor Failure Analysis (4 papers), Advanced Memory and Neural Computing (4 papers) and Electronic Packaging and Soldering Technologies (4 papers). The work is most often cited by research in Hardware and Architecture (283 citations), Electrical and Electronic Engineering (531 citations), Computer Networks and Communications (130 citations), Automotive Engineering (14 citations) and Biomedical Engineering (35 citations). John Barth has collaborated with scholars based in United States, France and Germany. Frequent co-authors include Subramanian S. Iyer, Paul Parries, Erik Nelson, Toshiaki Kirihata, William R. Reohr, Charles H. Stapper, Dennis Hoyniak, Hillery C. Hunter, John W. Golz and Steven M. Burns. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IBM Journal of Research and Development, Journal of Low Power Electronics and Applications, Symposium on VLSI Technology and Integrated circuits and systems.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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