Pulkit Jain

2.8k citations

60 papers · 2.1k · 2 hit papers · h-index 17

Impact in

Hardware and Architecture top 2%
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 2%
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design

Papers in

Electrical and Electronic Engineering 35
- Semiconductor materials and devices 22
- Advancements in Semiconductor Devices and Circuit Design 16
- Ferroelectric and Negative Capacitance Devices 9
- Advanced Memory and Neural Computing 7
- Low-power high-performance VLSI design 6
- IoT-based Smart Home Systems 4
- 3D IC and TSV technologies 3
Hardware and Architecture 4

Co-authors: Chris H. Kim (16 shared papers)Ki Chul Chun (8 shared papers)Fatih Hamzaoglu (4 shared papers)Jung Hwa Lee (2 shared papers)Shanshan Xie (3 shared papers)Jaydeep P. Kulkarni (3 shared papers)Taeho Kim (2 shared papers)Aseem Sayal (2 shared papers)
Journals: IEEE Journal of Solid-State Circuits (4 papers)Journal of Tribology (1 paper)International Journal of Asian Business and Information Management (1 paper)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)Computers, materials & continua/Computers, materials & continua (Print) (1 paper)
Partner nations: United States India South Korea

In The Last Decade

Pulkit Jain

55 papers receiving 2.1k citations

Pulkit Jain's Hit Papers

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A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size 2014 · 452 citations

What are hit papers?

Paper score: A paper's citations measured against the top-1% bar of its own field and year: the square root of citations ÷ bar, so 1 means right at the bar and 2 means four times its citations. The bar blends the citation counts that enter the top 1% of the paper's subfields in its year (weighted 89.5%), of those subfields over all years (0.5%) and of its year across all fields (10%); a subfield and year with fewer than 400 papers takes its year's bar. Papers from 2026 are not scored yet: in an unfinished year, when a paper appeared matters more than how it is cited.

Hit paper: A paper cited at least 1.5× the top-1% bar of its field and year: a paper score of at least √1.5.

2014 A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
2007 A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

Peers

Countries citing papers authored by Pulkit Jain

Since Specialization

Citations

This map shows the geographic impact of Pulkit Jain's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Pulkit Jain with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Pulkit Jain more than expected).

Fields of papers citing papers by Pulkit Jain

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Pulkit Jain. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Pulkit Jain. The network helps show where Pulkit Jain may publish in the future.

Co-authors

The 25 scholars most cited alongside Pulkit Jain, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Pulkit Jain Line = papers co-authored together Pulkit Jain links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 60 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging Kajal Mistry, Robert S. Chau, Changhwan Choi, G. Ding, K. Fischer, Tahir Ghani, R. Grover, Won Seok Han Hit paper breakdown →	2007	649
2	A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S. Natarajan, M. Agostinelli, Sheikh Ali Akbar, M. C. Bost, Anupama Bowonder, Vinay Chikarmane, Siddharth Chouksey, Avirup Dasgupta Hit paper breakdown →	2014	452
3	16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	2021	120
4	13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique IEEE Conference Proceedings ·Liqiong Wei, Juan G. Alzate, Ümüt Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka	2019	116
5	13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V Pulkit Jain, Umut Ece ARSLAN, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty	2019	109
6	A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches IEEE Journal of Solid-State Circuits ·Ki Chul Chun, Pulkit Jain, Taeho Kim, Chris H. Kim	2011	94
7	A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches IEEE Journal of Solid-State Circuits ·Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim	2011	93
8	Non-Volatile RRAM Embedded into 22FFL FinFET Technology Oleg Golonzka, Ümüt Arslan, Mark T. Bohr, O. Baykan, Yao‐Feng Chang, Akshay Sanjay Chaudhari, A. Chen, James Stanier Clarke	2019	63
9	Agrovoltaics: Step towards sustainable energy-food combination Bioresource Technology Reports ·Pulkit Jain, Gautam Raina, Sunanda Sinha, Prashant Malik, Siddharth Mathur	2021	52
10	Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing K. Fischer, M. Agostinelli, Cifford Allen, David F. Bahr, M. C. Bost, Peter K. Charvat, Vinay Chikarmane, Qundong Fu	2015	50
11	A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor IEEE Journal of Solid-State Circuits ·Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim	2012	36
12	Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) ·Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	2022	32
13	A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, Chris H. Kim	2009	28
14	A 1.1V, 667MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110µsec Ki Chul Chun, Pulkit Jain, Taeho Kim, Chris H. Kim	2010	18
15	Thermal and Power Delivery Challenges in 3D ICs Integrated circuits and systems ·Pulkit Jain, Pingqiang Zhou, Chris H. Kim, Sachin S. Sapatnekar	2009	18
16	Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design IEEE Micro ·Xiaofei Wang, John P. Keane, Tony Tae -Hyoung Kim, Pulkit Jain, Qianying Tang, Chris H. Kim	2014	17
17	eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters IEEE Journal of Solid-State Circuits ·Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	2023	17
18	A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim	2011	13
19	Impact of interconnect length on BTI and HCI induced frequency degradation Xiaofei Wang, Pulkit Jain, Dong Jiao, Chris H. Kim	2012	12
20	Automated Identification Algorithm Using CNN for Computer Vision in Smart Refrigerators Computers, materials & continua/Computers, materials & continua (Print) ·Pulkit Jain, Paras Chawla, Mehedi Masud, Shubham Mahajan, Amit Kant Pandit	2021	11

About Pulkit Jain

Pulkit Jain is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Electronic, Optical and Magnetic Materials, Signal Processing and Computer Vision and Pattern Recognition, having authored 60 papers that have together received 2.1k indexed citations. Recurring topics across this work include Semiconductor materials and devices (22 papers), Advancements in Semiconductor Devices and Circuit Design (16 papers), Ferroelectric and Negative Capacitance Devices (9 papers), Advanced Memory and Neural Computing (7 papers), Low-power high-performance VLSI design (6 papers), Copper Interconnects and Reliability (5 papers), IoT-based Smart Home Systems (4 papers) and 3D IC and TSV technologies (3 papers). The work is most often cited by research in Hardware and Architecture (250 citations), Electrical and Electronic Engineering (1.9k citations), Atomic and Molecular Physics, and Optics (184 citations), Computer Networks and Communications (132 citations) and Materials Chemistry (218 citations). Pulkit Jain has collaborated with scholars based in United States, India and South Korea. Frequent co-authors include Chris H. Kim, Ki Chul Chun, Fatih Hamzaoglu, Jung Hwa Lee, Shanshan Xie, Jaydeep P. Kulkarni, Taeho Kim, Aseem Sayal, Wei Zhang and Prashant Malik. Their work appears in journals such as IEEE Journal of Solid-State Circuits, Journal of Tribology, International Journal of Asian Business and Information Management, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Computers, materials & continua/Computers, materials & continua (Print).

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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Pulkit Jain

Pulkit Jain's Hit Papers

Peers

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Fields of papers citing papers by Pulkit Jain

All Works

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