K.H. Pan

535 citations
9 papers · 428 · h-index 9

Impact in

  • Electrical and Electronic Engineering top 10%
    • Advancements in Semiconductor Devices and Circuit Design
    • Low-power high-performance VLSI design
    • Semiconductor materials and devices
    • VLSI and FPGA Design Techniques
    • 3D IC and TSV technologies
    • Advanced Memory and Neural Computing
  • Hardware and Architecture top 10%
    • Parallel Computing and Optimization Techniques

Papers in

Journals
Technical digest - International Electron Devices Meeting/Technical digest (6 papers)IEEE Symposium on VLSI Technology (1 paper)Symposium on VLSI Technology (2 papers)
Partner nations
Taiwan

In The Last Decade

K.H. Pan

9 papers receiving 412 citations

Peers

K.H. Pan
Comparison fields: 5 of 20
  • Electrical and Electronic Engineering 351
  • Hardware and Architecture 33
  • Biomedical Engineering 34
  • Materials Chemistry 22
  • Computer Networks and Communications 9
Replace K.S. Chen with:
K.S. Chen Taiwan
M.C. Chiang Taiwan
Vincent S. Chang Taiwan
R.F. Tsui Taiwan
Jinke Chen Taiwan
C. W. Chang Taiwan
T. Miyashita Japan
J.Y. Cheng Taiwan
Shien-Yang Michael Wu Taiwan
Nadine Azémard France
K.H. Pan relative to K.S. Chen Taiwan K.S. Chen's profile →
Citations per field
00.5×1.5×
K.S. Chen · 1×
Citations per year

Countries citing papers authored by K.H. Pan

Since Specialization
Citations

This map shows the geographic impact of K.H. Pan's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K.H. Pan with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K.H. Pan more than expected).

Fields of papers citing papers by K.H. Pan

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K.H. Pan. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K.H. Pan. The network helps show where K.H. Pan may publish in the future.

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All Works

9 of 9 papers shown
#Work
1
A 16nm FinFET CMOS technology for mobile SoC and computing applications
Technical digest - International Electron Devices Meeting/Technical digest ·Shien-Yang Michael Wu, Chi-Hsien Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, Shixuan Yang, Mong Song Liang, T. Miyashita
2013128
2
A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications
Technical digest - International Electron Devices Meeting/Technical digest ·Shien-Yang Michael Wu, C.Y. Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, Shixuan Yang, C.H. Tsai, P.N. Chen
2016106
3
An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
Technical digest - International Electron Devices Meeting/Technical digest ·Shien-Yang Michael Wu, C.Y. Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, Shixuan Yang, Shu-Wei Chang, T. Miyashita
201456
4
A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications
Technical digest - International Electron Devices Meeting/Technical digest ·Shien-Yang Michael Wu, Yeong‐Hwa Chang, M.C. Chiang, C.Y. Lin, J.J. Liaw, Jiang-Hong Cheng, J.-Y. Yeh, H.F. Chen
202240
5
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
Symposium on VLSI Technology ·Shien-Yang Michael Wu, J.J. Liaw, Chih-Yung Lin, M.C. Chiang, J.Y. Cheng, Ming-Hsien Tsai, Ming-Che Liu, Po-Yi Wu
200632
6
Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
Technical digest - International Electron Devices Meeting/Technical digest ·Chih‐Hao Chang, Vincent S. Chang, K.H. Pan, K.T. Lai, Jing-Ruei Lu, J.A. Ng, C.Y. Chen, Bang-Li Wu
202223
7
Demonstration of a sub-0.03 um2high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node
IEEE Symposium on VLSI Technology ·Shien-Yang Michael Wu, C.Y. Lin, M.C. Chiang, J.J. Liaw, J.Y. Cheng, Chih-Sheng Chang, Vincent S. Chang, K.H. Pan
201618
8
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM
Technical digest - International Electron Devices Meeting/Technical digest ·Shien-Yang Michael Wu, Chung-Cheng Chou, C.Y. Lin, M.C. Chiang, Chengyi Yang, Ming-Che Liu, Lili Hu, Chih-Sheng Chang
200713
9
A highly manufacturable 0.25 μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology
Symposium on VLSI Technology ·Min-Hua Chang, J.K. Ting, J.S. Shy, Liang-Rong Chen, C.W. Liu, Jun Wu, K.H. Pan, Chih-Wei Tu
200212

About K.H. Pan

K.H. Pan is a scholar working on Electrical and Electronic Engineering, Nuclear Energy and Engineering, Waste Management and Disposal, Infectious Diseases and Organic Chemistry, having authored 9 papers that have together received 428 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (8 papers), Low-power high-performance VLSI design (5 papers) and Semiconductor materials and devices (1 paper). The work is most often cited by research in Electrical and Electronic Engineering (351 citations), Hardware and Architecture (33 citations), Biomedical Engineering (34 citations), Materials Chemistry (22 citations) and Computer Networks and Communications (9 citations). K.H. Pan has collaborated with scholars based in Taiwan. Their work appears in journals such as Technical digest - International Electron Devices Meeting/Technical digest, IEEE Symposium on VLSI Technology and Symposium on VLSI Technology.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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