I‐Chyn Wey

479 citations

57 papers · 337 · h-index 11

Impact in

Hardware and Architecture top 10%
- VLSI and Analog Circuit Testing
Electrical and Electronic Engineering
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies

Papers in

Electrical and Electronic Engineering 49
- Low-power high-performance VLSI design 32
- Radiation Effects in Electronics 18
- Advancements in Semiconductor Devices and Circuit Design 12
- Advancements in PLL and VCO Technologies 7
- Semiconductor materials and devices 7
- Advanced Memory and Neural Computing 7
Biomedical Engineering 19
- Analog and Mixed-Signal Circuit Design 18

Co-authors: An-Yeu Wu (12 shared papers)Jie Chen (8 shared papers)Lili Lin (1 shared paper)Kambiz Moez (2 shared papers)Tee Hui Teo (10 shared papers)Yu-Sheng Yang (1 shared paper)Mohamad Sawan (1 shared paper)Wei Wang (1 shared paper)
Journals: International Journal of Circuit Theory and Applications (3 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (3 papers)Sensors (2 papers)IEEE Transactions on Circuits and Systems I Regular Papers (2 papers)IEEE Transactions on Circuits & Systems II Express Briefs (1 paper)
Partner nations: Taiwan Singapore Canada

In The Last Decade

I‐Chyn Wey

51 papers receiving 304 citations

Peers

Countries citing papers authored by I‐Chyn Wey

Since Specialization

Citations

This map shows the geographic impact of I‐Chyn Wey's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by I‐Chyn Wey with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites I‐Chyn Wey more than expected).

Fields of papers citing papers by I‐Chyn Wey

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by I‐Chyn Wey. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by I‐Chyn Wey. The network helps show where I‐Chyn Wey may publish in the future.

Co-authors

The 25 scholars most cited alongside I‐Chyn Wey, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with I‐Chyn Wey Line = papers co-authored together I‐Chyn Wey links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Showing the 20 most-cited of 57 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term Lecture notes in computer science ·I‐Chyn Wey, Cheng-Chen Ho, Yi‐Sheng Lin, Chien-Chang Peng	2012	41
2	A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process IEEE Transactions on Circuits & Systems II Express Briefs ·Xiaojian Yu, Kambiz Moez, I‐Chyn Wey, Mohamad Sawan, Jie Chen	2016	25
3	Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits IEEE Transactions on Circuits and Systems I Regular Papers ·I‐Chyn Wey, You-Gang Chen, Changhong Yu, An-Yeu Wu, Jie Chen	2009	22
4	Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification Signal Image and Video Processing ·Lili Lin, I‐Chyn Wey, Jinghua Ding	2014	19
5	A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design Microelectronics Journal ·I‐Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng	2013	19
6	Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·I‐Chyn Wey, Chien-Chang Peng, Feng-Yu Liao	2014	16
7	Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·I‐Chyn Wey, Chun-Chien Wang	2011	15
8	A Scalable DCO Design for Portable ADPLL Designs NTUR (臺灣機構典藏) ·Chia-Tsun Wu, Wei Wang, I‐Chyn Wey, An-Yeu Wu	2005	14
9	A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement I‐Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, An-Yeu Wu	2006	13
10	Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique International Journal of Circuit Theory and Applications ·I‐Chyn Wey, Chun‐Wei Chang, Yu‐Cheng Liao, Heng‐Jui Chou	2014	11
11	A 3.3 V 1 GHz high speed pipelined Booth multiplier Hwang‐Cherng Chow, I‐Chyn Wey	2003	11
12	All digital folded low‐area, low‐power maximum power point tracking chip for photovoltaic energy conversion system International Journal of Circuit Theory and Applications ·I‐Chyn Wey, Shu‐Hao Kuo	2013	9
13	A new low-voltage CMOS 1-bit full adder for high performance applications I‐Chyn Wey, Chun-Hua Huang, Hwang‐Cherng Chow	2003	8
14	Complex Human Activities Recognition Based on High Performance 1D CNN Model Raman Maurya, Tee Hui Teo, Shi Hui Chua, Hwang‐Cherng Chow, I‐Chyn Wey	2022	7
15	Design and Verification of a New Universal Active Filter Based on the Current Feedback Operational Amplifier and Commercial AD844 Integrated Circuit Sensors ·Hua‐Pin Chen, I‐Chyn Wey, Liang-Yen Chen, Cheng-Yueh Wu, San-Fu Wang	2023	6
16	Systolic Array Based Convolutional Neural Network Inference on FPGA Shi Hui Chua, Tee Hui Teo, Mulat Ayinet Tiruye, I‐Chyn Wey	2022	6
17	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency Sung-Tze Wu, Chih-Hao Chao, I‐Chyn Wey, An-Yeu Wu	2007	6
18	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder Hwang‐Cherng Chow, I‐Chyn Wey	2003	6
19	A clock-fault tolerant architecture and circuit for reliable nanoelectronics system Woon Tiong Ang, Hui Fei Rao, Changhong Yu, Jilin Liu, I‐Chyn Wey, An-Yeu Wu, Hong Zhao, Jie Chen	2007	5
20	Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits Integration ·I‐Chyn Wey, Ye-Jhih Shen	2014	5

About I‐Chyn Wey

I‐Chyn Wey is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Computer Networks and Communications, Computer Vision and Pattern Recognition and Hardware and Architecture, having authored 57 papers that have together received 337 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (32 papers), Analog and Mixed-Signal Circuit Design (18 papers), Radiation Effects in Electronics (18 papers), Advancements in Semiconductor Devices and Circuit Design (12 papers), Advancements in PLL and VCO Technologies (7 papers), Semiconductor materials and devices (7 papers), Advanced Memory and Neural Computing (7 papers) and Advanced Neural Network Applications (6 papers). The work is most often cited by research in Hardware and Architecture (74 citations), Electrical and Electronic Engineering (292 citations), Computational Theory and Mathematics (43 citations), Biomedical Engineering (109 citations) and Signal Processing (20 citations). I‐Chyn Wey has collaborated with scholars based in Taiwan, Singapore and Canada. Frequent co-authors include An-Yeu Wu, Jie Chen, Lili Lin, Kambiz Moez, Tee Hui Teo, Yu-Sheng Yang, Mohamad Sawan, Wei Wang, Jie Chen and Chun‐Wei Chang. Their work appears in journals such as International Journal of Circuit Theory and Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Sensors, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Circuits & Systems II Express Briefs.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

I‐Chyn Wey

Impact in

Papers in i

In The Last Decade

I‐Chyn Wey

Peers

Countries citing papers authored by I‐Chyn Wey

Fields of papers citing papers by I‐Chyn Wey

All Works

About I‐Chyn Wey

Explore authors with similar magnitude of impact

Papers in