Amit Agarwal

3.8k citations

107 papers · 2.8k · h-index 25

Impact in

Hardware and Architecture top 0.5%
- Parallel Computing and Optimization Techniques
- Physical Unclonable Functions (PUFs) and Hardware Security
Electrical and Electronic Engineering top 2%
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis

Papers in

Hardware and Architecture 41
- Physical Unclonable Functions (PUFs) and Hardware Security 13
- Parallel Computing and Optimization Techniques 13
Electrical and Electronic Engineering 69
- Low-power high-performance VLSI design 39
- Semiconductor materials and devices 27
- Advancements in Semiconductor Devices and Circuit Design 22
- Advanced Memory and Neural Computing 12
- Radiation Effects in Electronics 11

Co-authors: Kaushik Roy (23 shared papers)Ram Kumar Krishnamurthy (60 shared papers)Mark A Anders (57 shared papers)Himanshu Kaul (52 shared papers)Sanu K. Mathew (51 shared papers)Steven Hsu (43 shared papers)Sudhir K. Satpathy (26 shared papers)Bipul C. Paul (5 shared papers)
Journals: IEEE Journal of Solid-State Circuits (13 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (4 papers)IEEE Solid-State Circuits Letters (2 papers)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (1 paper)IEEE Transactions on Computers (1 paper)
Partner nations: United States India United Kingdom

In The Last Decade

Amit Agarwal

102 papers receiving 2.7k citations

Peers

Countries citing papers authored by Amit Agarwal

Since Specialization

Citations

This map shows the geographic impact of Amit Agarwal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Amit Agarwal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Amit Agarwal more than expected).

Fields of papers citing papers by Amit Agarwal

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Amit Agarwal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Amit Agarwal. The network helps show where Amit Agarwal may publish in the future.

Co-authors

The 25 scholars most cited alongside Amit Agarwal, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Amit Agarwal Line = papers co-authored together Amit Agarwal links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 107 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS Sanu K. Mathew, Sudhir K. Satpathy, Mark A Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram Kumar Krishnamurthy, Vivek K. De	2014	209
2	Near-threshold voltage (NTV) design Himanshu Kaul, Mark A Anders, Steven Hsu, Amit Agarwal, Ram Kumar Krishnamurthy, Shekhar Y. Borkar	2012	185
3	Reducing set-associative cache energy via way-prediction and selective direct-mapping Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Michael Duane Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy	2001	173
4	2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors IEEE Journal of Solid-State Circuits ·Sanu K. Mathew, Suresh Srinivasan, Mark A Anders, Himanshu Kaul, Steven K. Hsu, Farhana Sheikh, Amit Agarwal, Sudhir K. Satpathy, Ram Kumar Krishnamurthy	2012	162
5	A process-tolerant cache architecture for improved yield in nanoscale technologies IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Amit Agarwal, Bipul C. Paul, Hamid Mahmoodi, Animesh Datta, Kaushik Roy	2005	157
6	Process variation in embedded memories: failure analysis and variation aware architecture IEEE Journal of Solid-State Circuits ·Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy	2005	145
7	Gate leakage reduction for scaled devices using transistor stacking IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Subhas Chandra Mukhopadhyay, Cassondra Neau, Riza Tamer Cakici, Amit Agarwal, C.H. Kim, Kaushik Roy	2003	121
8	340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS IEEE Journal of Solid-State Circuits ·Sanu K. Mathew, Sudhir K. Satpathy, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory Chen, Ram Kumar Krishnamurthy	2015	120
9	A single-V/sub t/ low-leakage gated-ground cache for deep submicron IEEE Journal of Solid-State Circuits ·Amit Agarwal, Hai Helen Li, Kaushik Roy	2003	94
10	Leakage Power Analysis and Reduction for Nanoscale Circuits IEEE Micro ·Amit Agarwal, Subhas Chandra Mukhopadhyay, A. Raychowdhury, Krishnendu Roy, C.H. Kim	2006	93
11	Reducing set-associative cache energy via way-prediction and selective direct-mapping Michael Duane Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy	2005	91
12	An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS IEEE Journal of Solid-State Circuits ·Sudhir K. Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram Suresh, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Kumar Krishnamurthy, Vivek K. De	2019	86
13	$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS IEEE Journal of Solid-State Circuits ·Sanu K. Mathew, David J. Johnston, Sudhir K. Satpathy, Vikram Suresh, Paul Newman, Mark A Anders, Himanshu Kaul, Amit Agarwal, Steven K. Hsu, Gregory Chen, Ram Kumar Krishnamurthy	2016	85
14	Leakage power analysis and reduction: models, estimation and tools IEE Proceedings - Computers and Digital Techniques ·Amit Agarwal, Saibal Mukhopadhyay, C.H. Kim, Arijit Raychowdhury, Kaushik Roy	2005	47
15	Leakage in nano-scale technologies Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy	2004	45
16	A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS IEEE Journal of Solid-State Circuits ·Gregory Chen, Mark A Anders, Himanshu Kaul, Sudhir K. Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram Kumar Krishnamurthy, Vivek K. De, Shekhar Y. Borkar	2014	44
17	A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS Steven Hsu, Amit Agarwal, Mark A Anders, Sanu K. Mathew, Himanshu Kaul, Farhana Sheikh, Ram Kumar Krishnamurthy	2012	44
18	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS Himanshu Kaul, Mark A Anders, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Kumar Krishnamurthy, Shekhar Y. Borkar	2012	42
19	Low-power design techniques for scaled technologies Integration ·Bipul C. Paul, Amit Agarwal, Kaushik Roy	2005	35
20	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS IEEE Journal of Solid-State Circuits ·Himanshu Kaul, Mark A Anders, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram Kumar Krishnamurthy, Shekhar Y. Borkar	2010	34

About Amit Agarwal

Amit Agarwal is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Artificial Intelligence, Computer Vision and Pattern Recognition and Computer Networks and Communications, having authored 107 papers that have together received 2.8k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (39 papers), Semiconductor materials and devices (27 papers), Advancements in Semiconductor Devices and Circuit Design (22 papers), Physical Unclonable Functions (PUFs) and Hardware Security (13 papers), Parallel Computing and Optimization Techniques (13 papers), Advanced Memory and Neural Computing (12 papers), Cryptographic Implementations and Security (12 papers) and Radiation Effects in Electronics (11 papers). The work is most often cited by research in Hardware and Architecture (1.5k citations), Electrical and Electronic Engineering (2.0k citations), Computer Networks and Communications (535 citations), Computer Vision and Pattern Recognition (355 citations) and Computational Theory and Mathematics (205 citations). Amit Agarwal has collaborated with scholars based in United States, India and United Kingdom. Frequent co-authors include Kaushik Roy, Ram Kumar Krishnamurthy, Mark A Anders, Himanshu Kaul, Sanu K. Mathew, Steven Hsu, Sudhir K. Satpathy, Bipul C. Paul, Steven K. Hsu and T. N. Vijaykumar. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Solid-State Circuits Letters, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Computers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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